Compactest:为组合电路生成紧凑测试集的方法

1991, Proceedings. International Test Conference Pub Date : 1991-10-26 DOI:10.1109/TEST.1991.519510

I. Pomeranz, L. Reddy, S. Reddy

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引用次数: 434

摘要

提出了一种启发式方法来帮助推导用于检测组合逻辑电路中单个卡滞故障的小测试集。可以将启发式方法添加到现有的测试模式生成器中，而不会影响故障覆盖率。通过将所提出的启发式算法添加到简单的PODEM程序中，并将其应用于ISCAS-85和全扫描ISCAS-89基准电路，得到的实验结果证实了所提出的启发式算法的有效性。>

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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COMPACTEST: A METHOD TO GENERATE COMPACT TEST SETS FOR COMBINATIONAL CIRCUITS

Heuristics to aid the derivation of small test sets that detect single stuck-at faults in combinational logic circuits are proposed. The heuristics can be added to existing test pattern generators without compromising fault coverage. Experimental results obtained by adding the proposed heuristics to a simple PODEM procedure and applying it to the ISCAS-85 and fully-scanned ISCAS-89 benchmark circuits are presented to substantiate the effectiveness of the proposed heuristics. >

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1991, Proceedings. International Test Conference

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