{"title":"CONCURRENT ERROR DETECTION IN LINEAR ANALOG AND SWITCHED-CAPACITOR STATE VARIABLE SYSTEMS USING CONT","authors":"A. Chatterjee","doi":"10.1109/TEST.1991.519721","DOIUrl":"https://doi.org/10.1109/TEST.1991.519721","url":null,"abstract":"In this paper we study the problem of concurrent error detection in analog and switched-capacitor state variable systems. The errors can arise due to failed components (resistors, capacitors, opcrational amplifiers, etc) or simply due to line opens and shorts. A failed component is one whose value has changed due to a harsh environment (heat, etc) or due to drift or one which no longer performs its intended function (such as a shorted capacitor). The error detection is performed by a small amount of additional circuitry whose inputs are tapped directly from the outputs of all the operational amplifiers that compose the circuit on which error detection is to be performed. The sensitivity of the error detection circuitry to errors in the component values can be easily adjusted. The basic idea is to use continuous matrix chechums for error detection. This is possible because the function of an analog or switched-capacitor state variable system can be represented mathematically by a set of matrices to which checksum codes can be applied.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121981670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Minimal Test Sets for Combinational Circuits","authors":"G. Tromp","doi":"10.1109/TEST.1991.519511","DOIUrl":"https://doi.org/10.1109/TEST.1991.519511","url":null,"abstract":"Generating minimal test sets for combinational circuits is a NP-hard problem. In this paper it will be shown that for a class of circuits with a high fnult compatibility well-known test set compaction methods such as dynamic compaction and reverse order fault simulation do not effectively minimize the test set. Furthermore it will be shown for a number of benchmark circuits that it is possible to generate test sets that are significantly smaller than test sets generated by conventional test set compaction methods. This paper will also present an algorithm based on finding a maximal clique in a graph to estimate the size of a minimum test set.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127248958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Test Propagation Through Modules and Circuits","authors":"B. Murray, J. Hayes","doi":"10.1109/TEST.1991.519740","DOIUrl":"https://doi.org/10.1109/TEST.1991.519740","url":null,"abstract":"Test generation performance can be improved significantly over conventional techniques by combining precomputed module tests to form a test for a complete circuit. We introduce a theory of propagation for modules and circuits which can be used for hierarchical test generation and design for testability. The propagation characteristics of a module - whether it can be sensitized to propagate some or all possible fault effects on an input bus - are represented by structures called ambiguity sets. Algebraic operations are performed on ambiguity sets to determine the propagation characteristics of multi-module circuits. We show how this propagation theory is used in test generation and also to aid in designing circuits suitable for high-level test generation.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125842318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"CONCURRENT ERROR DETECTION FOR RESTRICTED FAULT SETS IN SEQUENTIAL CIRCUITS AND MICROPROGRAMMED CONT","authors":"Lawrence P. Holmquist, L. Kinney","doi":"10.1109/TEST.1991.519758","DOIUrl":"https://doi.org/10.1109/TEST.1991.519758","url":null,"abstract":"A methodology is developed using convolutional codes for on-line detection of sequencing errors in sequential circuits induced by any given set of transient faults. Key outputs are added to the machine. In the casc of microprogrammed control units, key bits are appended to each microinstruction. The keys are chosen such that all sequences of key outputs are code sequences in a convolutional code. Using an error-detecting decoder for the code, all transient sequencing errors resulting from faults in the fault set can be detected with latency not exceeding the latency distance of the convolutional code.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123252411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Looking for Functional Fault Equivalence","authors":"A. Lioy","doi":"10.1109/TEST.1991.519751","DOIUrl":"https://doi.org/10.1109/TEST.1991.519751","url":null,"abstract":"Recognition of test equivalent faults is usually applied to reduce the number of target faults for test generation and fault simulation. Also fault diagnosis benefits from this knowledge as it allows fast dropping of undistinguishable faults. Equivalent faults are generally identified by mean of a structural analysis of the circuit. Functionally equivalent faults are not considered as their identification is computationally too expensive for real circuits. This paper presents new theorems about functional fault equivalence and dominance. They provide a constructive basis upon which a functional fault collapsing algorithm is built. Application to a set of benchmark circuits establish that identification of functionally equivalent faults is feasible, and that their number may be a not negligible fraction of the faults in a circuit. Results apply both to combinational and synchronous sequential circuits.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"36 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123568329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"THE EFFECT OF DIFFERENT TEST SETS ON QUALITY LEVEL PREDICTION: WHEN IS 80% BETTER THAN 90%?","authors":"P. Maxwell, R. Aitken, V. Johansen, I. Chiang","doi":"10.1109/TEST.1991.519695","DOIUrl":"https://doi.org/10.1109/TEST.1991.519695","url":null,"abstract":"This paper discusses the use of stuck-at fault coverage as a means of determining quality levels. Data from a part tested with both functional and scan tests is analyzed and compared to three existing theories. It is shown that reasonable predictions of quality level are possible for the functional tests, but that scan tests produce significantly worse quality levels than predicted, Apparent clustering of defects resulted in very good quality levels for fault coverages less than 99%.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"193 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124329193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A CONCURRENT TEST ARCHITECTURE FOR MASSIVELY-PARALLEL COMPUTERS AND ITS ERROR DETECTION CAPABILITY","authors":"M. Hâncu, K. Iwasaki, Yuji Sato, M. Sugie","doi":"10.1109/TEST.1991.519741","DOIUrl":"https://doi.org/10.1109/TEST.1991.519741","url":null,"abstract":"New principles for the on-line system-level test of multiprocessors are proposed, based on signaturing and monitoring data dependences together with control dependences. I n order to help in this process, each data routing message contains both source and destination addresses. At each message source, the destination addresses of the outgoing messages are compressed. At the same time, at each destination, the source addresses of all incoming messages are compressed. Concurrent compression of the instructions executed by the PES is also possible. The resulting signatures are compared at the end of each computational block with reference signatures created at compilation time. An analytical model and an analysis for the address compression process used for the monitoring the data routing process are provided. The aliasing probability for the error detection process is studied, obtaining closedform expressions in the single error case and upper bounds in the multiple error case.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115067618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Barbara Cole, G. Herzog, P. Ngo, S. Hinkle, Peter Sherry
{"title":"STATISTICAL PRODUCT MONITORING: A POWERFUL TOOL FOR QUALITY IMPROVEMENT","authors":"Barbara Cole, G. Herzog, P. Ngo, S. Hinkle, Peter Sherry","doi":"10.1109/TEST.1991.519706","DOIUrl":"https://doi.org/10.1109/TEST.1991.519706","url":null,"abstract":"As the quality of integrated circuits has improved Statistical Product Monitoring, an over the last several years to 100 DPPM or less, it is no longer practical-for high volume users of low innovative test strategy, based on variables DPPM devices to rely on direct product testing to data collection, environmental stress control the quality of devices going into their products. This - paper reviews the use of screening, and statistical process control Statistical Product Monitoring (SPM) of significant component electrical parameters, to techniques, permits the development of develop a component quality strategy. The role of improved quality and reliability programs. While existing quality and reliability SPM in supplier qualification, selection, and continuous supplier monitoring is discussed. Practical examples from an on-line SPM system programs are used to determine the initial will be presented.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"1 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131366993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"THE BEHAVIOR AND TESTING IMPLICATIONS OF CMOS IC LOGIC GATE OPEN CIRCUITS","authors":"C. Henderson, J. Soden, C. Hawkins","doi":"10.1109/TEST.1991.519522","DOIUrl":"https://doi.org/10.1109/TEST.1991.519522","url":null,"abstract":"The electrical and test properties of several logic gate open circuit defect structures were measured. Results indicate that tunneling current across fine geometry discontinuities enables low frequency operation of ICs. No significant capacitive coupling was observed for adjacent metal interconnect or for large metal opens on the gate interconnects. These results indicate the need for different methods of open circuit defect detection during test. I. Introduct ion Structured test methods require thorough knowledge of the defects that cause failure. This study presents data on the electrical characteristics of a common CMOS IC defect, an input open circuit to a logic gate. Individual transistor gate terminal opens are not considered. Data show that logic gate input open circuit defects for narrow interconnect discontinuities allow circuit functionality at frequencies from DC into the MHz region. Evidence supports electron tunneling as the basic mechanism for circuit functionality in the presence of this type of defect. This suggests that the open-circuited logic gate defect should be treated as a delay fault in order to guarantee detection. Open circuit defects with wide dimensions exhibited no signal coupling. Data also show the conditions under which quiescent power supply current (IDD,) tests can detect open circuit logic gate inputs. In the late 1980s two groups fabricated circuits or tested existing circuits with specific types of open circuits [l, 21. Others studied transistor-level open circuit phenomena and proposed design changes to reduce the occurrence of opens [3, 41. It was demonstrated that some open circuits are not detected by conventional stuck-at test methodologies.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128531072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Built-in-self-test considerations in a high-performance, general-purpose processor","authors":"S. Sarma","doi":"10.1109/TEST.1991.519489","DOIUrl":"https://doi.org/10.1109/TEST.1991.519489","url":null,"abstract":"The intent of this paper is to describe the built-in-self-test (BIST) design and verification methodology followed for thermal conduction modules (TCMs) in the aircooled IBM Enterprise System/9000 Type 9121 processors. The ES/9121 processor utilizes a mixture of bipolar and CMOS circuitry. Each ES/9121 processor TCM can accommodate a maximum of 121 logic and memory chips. There are five distinct TCMs in the uniprocessor configuration and the testability results achieved using BIST will be presented in this paper. The resources required to support the BIST process will also be presented. Finally, improvements to the BIST methodology will be discussed.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129759822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}