Multi-Step Stress Test for Yield Improvement of 16Mbit EPROMs with Redundancy Scheme

Abstract

To reject defective cells and to guarantee device reliability in a short time, internal test circuits have been implemented in non-volatile memories. On the other hand, for high density EPROMs, implementing column redundancy scheme is of vital importance in order to obtain a reasonable yield, as inter-connection design rules are limiting the cell size. However, the conventional column redundancy scheme was not very efficient, because the test circuits did not work well for one of the most dominant failures on miniaturized cells. This paper proposes a new test algorithm, multi-step stress test to solve the problem. The concept has been applied to an actual 16Mbit EPROM, and the yield has been improved to almost double that at the time of the initial developing stage.