HIGH PERFORMANCE PIN ELECTRONICS EMPLOYING GaAs IC AND HYBRID CIRCUIT PACKAGING TECHNOLOGY

B. Baril, D. Clayson, D. McCracken, S. Taylor
{"title":"HIGH PERFORMANCE PIN ELECTRONICS EMPLOYING GaAs IC AND HYBRID CIRCUIT PACKAGING TECHNOLOGY","authors":"B. Baril, D. Clayson, D. McCracken, S. Taylor","doi":"10.1109/TEST.1991.519743","DOIUrl":null,"url":null,"abstract":"This paper describes the latest generation of pin electronics developed for a high-speed verification ATE system. The pin electronics sub-system provides a driverireceiver with outstanding bandwidth in addition to per-pin current loading and per-pin parametrics. A f.11 custom GaAs IC provides the major features and advanced performance of the driver, receiver, and current load. The combined modules use only 2.5 square inches of circuit board area per tester channel. This paper details the circuit design and measured perfor,mance of the GaAs IC and the three hybrid multichip rzwdules that complete the pin electronics Bnctions.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1991, Proceedings. International Test Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TEST.1991.519743","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3

Abstract

This paper describes the latest generation of pin electronics developed for a high-speed verification ATE system. The pin electronics sub-system provides a driverireceiver with outstanding bandwidth in addition to per-pin current loading and per-pin parametrics. A f.11 custom GaAs IC provides the major features and advanced performance of the driver, receiver, and current load. The combined modules use only 2.5 square inches of circuit board area per tester channel. This paper details the circuit design and measured perfor,mance of the GaAs IC and the three hybrid multichip rzwdules that complete the pin electronics Bnctions.
采用GaAs集成电路和混合电路封装技术的高性能引脚电子器件
本文介绍了为高速验证ATE系统开发的最新一代引脚电子器件。引脚电子子系统除了提供单引脚电流负载和单引脚参数外,还提供具有出色带宽的驱动接收器。f.11定制GaAs IC提供驱动、接收器和电流负载的主要特性和高级性能。每个测试通道的组合模块仅使用2.5平方英寸的电路板面积。本文详细介绍了GaAs集成电路的电路设计和测试性能,以及完成引脚电子功能的三个混合多芯片模块。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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