{"title":"高引脚数测试仪的计算机体系结构","authors":"Chris Hannaford","doi":"10.1109/TEST.1991.519772","DOIUrl":null,"url":null,"abstract":"A unique architectural feature of a new mixed signal tester is its processor per pin computer architecture. The system requirements that dictated the use of such an architecture are described. The hardware implementation is detailed, and the resultant system performance is examined. The use of the per pin processor for implementing novel functions is described.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"40 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A Computer Architecture for High Pin Count Testers\",\"authors\":\"Chris Hannaford\",\"doi\":\"10.1109/TEST.1991.519772\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A unique architectural feature of a new mixed signal tester is its processor per pin computer architecture. The system requirements that dictated the use of such an architecture are described. The hardware implementation is detailed, and the resultant system performance is examined. The use of the per pin processor for implementing novel functions is described.\",\"PeriodicalId\":272630,\"journal\":{\"name\":\"1991, Proceedings. International Test Conference\",\"volume\":\"40 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1991-10-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1991, Proceedings. International Test Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/TEST.1991.519772\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1991, Proceedings. International Test Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TEST.1991.519772","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Computer Architecture for High Pin Count Testers
A unique architectural feature of a new mixed signal tester is its processor per pin computer architecture. The system requirements that dictated the use of such an architecture are described. The hardware implementation is detailed, and the resultant system performance is examined. The use of the per pin processor for implementing novel functions is described.