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2020 International SoC Design Conference (ISOCC)最新文献

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Performance Optimization of Silicon Photonic Ring Switch with CMOS Driver 带CMOS驱动器的硅光子环形开关的性能优化
2020 International SoC Design Conference (ISOCC) Pub Date : 2020-10-21 DOI: 10.1109/ISOCC50952.2020.9332951
Dae-Won Rho, Minkyu Kim, Hyun-Kyu Kim, W. Choi
{"title":"Performance Optimization of Silicon Photonic Ring Switch with CMOS Driver","authors":"Dae-Won Rho, Minkyu Kim, Hyun-Kyu Kim, W. Choi","doi":"10.1109/ISOCC50952.2020.9332951","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9332951","url":null,"abstract":"Crosstalk and insertion loss of a Si photonic 2 × 2 ring switch are optimized and a CMOS circuit that can control this ring switch is designed.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133091120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Adaptive Battery State-of-Charge Estimation Method for Electric Vehicle Battery Management System 电动汽车电池管理系统中电池电量状态自适应估计方法
2020 International SoC Design Conference (ISOCC) Pub Date : 2020-10-21 DOI: 10.1109/ISOCC50952.2020.9332950
Min-Joon Kim, Sung-Hun Chae, Yeonsoo Moon
{"title":"Adaptive Battery State-of-Charge Estimation Method for Electric Vehicle Battery Management System","authors":"Min-Joon Kim, Sung-Hun Chae, Yeonsoo Moon","doi":"10.1109/ISOCC50952.2020.9332950","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9332950","url":null,"abstract":"In this paper, an adaptive battery state-of-charge (SOC) estimation method for electric vehicle (EV) battery management system (BMS) is presented. In these days, many parts of EV have been developed with electrical systems, and it makes a growth of energy storage system named battery. Therefore, to make many type of batteries safer and more reliable, BMS is employed and implemented together in EV. The BMS monitors many kinds of battery states and is responsible to manage its charging and discharging. SOC is a key parameter in judging by BMS, and therefore it is certainly important to estimate the SOC accurately. Many SOC estimation methods have been studied, and extended Kalman-filter (EKF) based methods show the best performance. However, they have high computation complexity. In this paper, adaptively combination of EKF and conventional Coulomb counting method is proposed. Finally, the proposed adaptive method shows within 2% error with 70% decreased complexity compared to EKF.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133705007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Early Image Termination Technique During STDP Training of Spiking Neural Network 脉冲神经网络STDP训练中的早期图像终止技术
2020 International SoC Design Conference (ISOCC) Pub Date : 2020-10-21 DOI: 10.1109/ISOCC50952.2020.9333081
Dongwoo Lew, Jongsun Park
{"title":"Early Image Termination Technique During STDP Training of Spiking Neural Network","authors":"Dongwoo Lew, Jongsun Park","doi":"10.1109/ISOCC50952.2020.9333081","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333081","url":null,"abstract":"Spiking Neural Network (SNN) is a breed of neural networks that seek to achieve low energy and power by more closely mimicking biological brains. SNNs are often trained using lightweight unsupervised learning such as Spike Time Dependent Plasticity (STDP). However, STDP is prone to redundant time steps during training since STDP cannot determine current image needs further training or not. To reduce redundant time steps and lower energy costs during STDP training, we propose a novel technique that terminates training upon an image preemptively. The proposed technique reduces time steps by 44% with accuracy drop of 0.91% on MNIST.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132858043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
CAN Security Protocol Using Modified MAC 安全协议是否可以使用修改后的MAC
2020 International SoC Design Conference (ISOCC) Pub Date : 2020-10-21 DOI: 10.1109/ISOCC50952.2020.9332998
Do-Yeon Hwang, Yeonjin Kim, Jin-Gyun Chung
{"title":"CAN Security Protocol Using Modified MAC","authors":"Do-Yeon Hwang, Yeonjin Kim, Jin-Gyun Chung","doi":"10.1109/ISOCC50952.2020.9332998","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9332998","url":null,"abstract":"Controller area network (CAN) was developed by Bosch in the early 1980s. CAN has been widely applied due to its high reliability and low cost. In 2012, the standard for WLAN-based vehicle to everything(V2X) was published in IEEE, and V2X is steadily evolving. As V2X advances, the possibility of security attacks in vehicles has increased. However, security issues are not being addressed properly in CAN. In this paper, we propose an improved security protocol based on a data compression algorithm.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116579530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Reduced power consumption Current-mode ADC using SAR logic for AI application 采用SAR逻辑的AI应用电流模式ADC
2020 International SoC Design Conference (ISOCC) Pub Date : 2020-10-21 DOI: 10.1109/ISOCC50952.2020.9332945
Soyoun Park, Hyungmin Kim, D. Lee, Taemin Nho, Seongkweon Kim, D. Shim
{"title":"Reduced power consumption Current-mode ADC using SAR logic for AI application","authors":"Soyoun Park, Hyungmin Kim, D. Lee, Taemin Nho, Seongkweon Kim, D. Shim","doi":"10.1109/ISOCC50952.2020.9332945","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9332945","url":null,"abstract":"This paper introduces a new SAR logic that does not need to refer to the upper digital bits to overcome the limitation that the speed can be limited by the conversion time of the comparator by using conventional SAR logic. This proposed logic can be applied to a current-mode flash type ADC and it can be realized with a system consisting of current comparators, encoders and an input generator made up of current rectifiers. The proposed circuit has been implemented using 0.18-um CMOS technology. This circuit operates at a supply voltage of 3.3-V and its input current range is 0–100 μA. The active layout area of the 6-bit current-mode ADC is 341-μm×158 μm, The power consumption is estimated to be 2.4-mW when the input frequency is 100 kHz.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116582210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Simple Reference Voltage Generation Circuit Insensitive to Temperature 简单的参考电压产生电路对温度不敏感
2020 International SoC Design Conference (ISOCC) Pub Date : 2020-10-21 DOI: 10.1109/ISOCC50952.2020.9332938
Lei Sha, A. Kuwana, M. Horiguchi, Haruo Kobayashi
{"title":"Simple Reference Voltage Generation Circuit Insensitive to Temperature","authors":"Lei Sha, A. Kuwana, M. Horiguchi, Haruo Kobayashi","doi":"10.1109/ISOCC50952.2020.9332938","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9332938","url":null,"abstract":"This paper describes a reference voltage generation circuit insensitive to temperature, based on the MOSFET drain current temperature characteristics. The proposed circuit uses series connection of diode connected MOSFETs. As the temperature rises, the gate-source voltage of the diode connected MOSFET increases for large current per unit channel width whereas it decreases for small current. Hence when both MOSFETs are connected in series, their gate-source voltages are added, which can have small temperature coefficient. Based on this principle, a reference voltage insensitive to temperature can be generated.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129117741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Novel Scheme to Map Convolutional Networks to Network-on-Chip with Computing-In-Memory Nodes 一种将卷积网络映射到具有内存计算节点的片上网络的新方案
2020 International SoC Design Conference (ISOCC) Pub Date : 2020-10-21 DOI: 10.1109/ISOCC50952.2020.9332940
Jiayi Liu, Kejie Huang
{"title":"A Novel Scheme to Map Convolutional Networks to Network-on-Chip with Computing-In-Memory Nodes","authors":"Jiayi Liu, Kejie Huang","doi":"10.1109/ISOCC50952.2020.9332940","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9332940","url":null,"abstract":"Computing-In Memory (CIM) has been widely used to accelerate the inferencing speed of deep learning. Network-on-Chips (NoCs) are usually used together with CIM to enable the versatile ability of the hardware. This paper proposes a bandwidth aware mapping scheme to minimize both hops and bandwidth requirement. The simulation results show that the proposed scheme could reduce the hops and bandwidth requirements by more than 33.57% and 46.13%, respectively.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127924660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Asymmetric Prefetching Architecture for Multicore Processor 多核处理器的非对称预取结构
2020 International SoC Design Conference (ISOCC) Pub Date : 2020-10-21 DOI: 10.1109/ISOCC50952.2020.9332921
Duheon Choi, Kwangsub Kim, Eui-Young Chung
{"title":"Asymmetric Prefetching Architecture for Multicore Processor","authors":"Duheon Choi, Kwangsub Kim, Eui-Young Chung","doi":"10.1109/ISOCC50952.2020.9332921","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9332921","url":null,"abstract":"Prefetching is one of the main techniques for improving the performance of modern processors. Various prefetch algorithms have been proposed targeting various applications and memory access patterns. Modern SoCs are mainly equipped with multicore processors, and various processes are operated separately by each core. This implies that for each core, different prefetcher may work better. In this paper, we propose a hardware prefetcher that integrates three prefetching algorithms and statically allocates a prefetching algorithm that provides better performance to each workload in a multicore processor. We observe 4.6% overall performance improvement compared to using a single prefetcher and reduce buffer resources by 41%.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117215540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An Ultra-Low Power Wake-up Receiver Digital Controller for 5.8 GHz DSRC Applications 一种用于5.8 GHz DSRC应用的超低功耗唤醒接收机数字控制器
2020 International SoC Design Conference (ISOCC) Pub Date : 2020-10-21 DOI: 10.1109/ISOCC50952.2020.9332967
Imran Ali, Muhammad Asif, Huo Yingge, M. R. Rehman, Kangyoon Lee
{"title":"An Ultra-Low Power Wake-up Receiver Digital Controller for 5.8 GHz DSRC Applications","authors":"Imran Ali, Muhammad Asif, Huo Yingge, M. R. Rehman, Kangyoon Lee","doi":"10.1109/ISOCC50952.2020.9332967","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9332967","url":null,"abstract":"In this paper, an ultra-low power digital controller for 5.8 GHz dedicated short-range communication (DSRC) radio frequency (RF) wake-up receiver (WuRx) is proposed. It improves WuRx reliability, accuracy and enhances battery life by filtering non-wake-up signals. The digital hysteresis is introduced for configurable valid wake-up signal frequency range identification. The programmable successive number of valid wake-up signal cycles are confirmed before generating wake-up interrupt. From 0.9 V supply, it draws 38.5 nA current and consumes only 34.65 nW power. The configurable controller is fully synthesizable, requires 786 gates for its implementation in 130 nm CMOS process with 90 × 80 μm2chip area.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123410867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Improving Analysis Coverage for Dynamic IR Drop Sign-off in FinFET SoC Design 改进FinFET SoC设计中动态IR降信号的分析覆盖率
2020 International SoC Design Conference (ISOCC) Pub Date : 2020-10-21 DOI: 10.1109/ISOCC50952.2020.9332987
Minji Lee, Changseok Choi, Donghyeon Seo, Byeongjun Bang, Yongseok Kang, Woohyun Paik
{"title":"Improving Analysis Coverage for Dynamic IR Drop Sign-off in FinFET SoC Design","authors":"Minji Lee, Changseok Choi, Donghyeon Seo, Byeongjun Bang, Yongseok Kang, Woohyun Paik","doi":"10.1109/ISOCC50952.2020.9332987","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9332987","url":null,"abstract":"Power grid design is one of the key challenges in large SoC design. In order to guarantee robustness of the power grid, dynamic IR drop should be analyzed correctly. In this paper, we have described weakness of vectorless analysis and necessity of vector-based analysis. We have improved analysis coverage for the more accurate dynamic IR drop analysis. The analysis results were obtained with the FinFET technology node and all simulations were done in the ANSYS RedHawk.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132012461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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