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2020 International SoC Design Conference (ISOCC)最新文献

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Instant and Accurate Instance Segmentation Equipped with Path Aggregation and Attention Gate 基于路径聚合和注意门的快速准确的实例分割
2020 International SoC Design Conference (ISOCC) Pub Date : 2020-10-21 DOI: 10.1109/ISOCC50952.2020.9332981
Seung Il Lee, Hyun Kim
{"title":"Instant and Accurate Instance Segmentation Equipped with Path Aggregation and Attention Gate","authors":"Seung Il Lee, Hyun Kim","doi":"10.1109/ISOCC50952.2020.9332981","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9332981","url":null,"abstract":"With the development of GPU and deep learning, there has been great advances in the field of object detection and segmentation. Instance segmentation is one of the most important tasks used in many areas including autonomous vehicles and video surveillance because such areas require both high frames per second (FPS) and high accuracy. In this paper, we propose a method of attaching path aggregation network and attention gate based on real-time instance segmentation model, YOLACT, to increase the accuracy of instance segmentation. As a result of applying the proposed method to the YOLACT framework, the processing speed drops slightly by 2.7%, but the accuracy increases significantly up to 1.4AP, while still maintaining realtime processing of 32.6FPS.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113979098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An Energy-Efficient Imprecise Adder with a Lower-part Constant Approximation 具有下半常数近似的节能不精确加法器
2020 International SoC Design Conference (ISOCC) Pub Date : 2020-10-21 DOI: 10.1109/ISOCC50952.2020.9332922
Hyoju Seo, Yoon Seok Yang, Yongtae Kim
{"title":"An Energy-Efficient Imprecise Adder with a Lower-part Constant Approximation","authors":"Hyoju Seo, Yoon Seok Yang, Yongtae Kim","doi":"10.1109/ISOCC50952.2020.9332922","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9332922","url":null,"abstract":"This paper proposes a novel approximate adder that significantly reduces power and energy consumption by leveraging a lower-part constant scheme. When implemented with a 32-nm CMOS technology, the proposed adder reduces area, power, power-delay product, energy-delay product, and area-delay product, respectively, of 43%, 49%, 76%, 89%, and 73% compared to the ripple carry adder that is a traditional precise adder. Also, we demonstrate that our adder design can remarkably reduce power and energy consumption of digital image processing applications while obtaining an acceptable output image quality.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124351110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A Voting Phase Detector Design with Mitigated Process Variation 一种过程变化较小的投票鉴相器设计
2020 International SoC Design Conference (ISOCC) Pub Date : 2020-10-21 DOI: 10.1109/ISOCC50952.2020.9333007
Derek Lin, Jun-Yu Yang, Shi-Yu Huang
{"title":"A Voting Phase Detector Design with Mitigated Process Variation","authors":"Derek Lin, Jun-Yu Yang, Shi-Yu Huang","doi":"10.1109/ISOCC50952.2020.9333007","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333007","url":null,"abstract":"A Phase Detector is an indispensable component in a Delay-Locked Loop (DLL). It compares the phases of two input clock signals and then produce a binary lead/lag signal to indicate which clock signal arrives earlier. The resolution of a PD often determines the accuracy of a DLL in terms of the phase error. Unfortunately, a traditional cell-based PD is strongly susceptible to the process variation. In this paper, we propose a “Voting PD design” to alleviate this problem. First, a number of primitive phase detectors are incorporated, and then their primitive results undergo a majority voting process to produce the final lead/lag signal, and thereby enhancing the overall resolution. A statistical approximation shows that process variation can be compressed to 53% using a voting group of 5 primitive phase detectors.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128974923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Calibration of M-Channel Time-Interleaved Analog-to-Digital Converters Based on Curve Fitting 基于曲线拟合的m通道时间交错模数转换器标定
2020 International SoC Design Conference (ISOCC) Pub Date : 2020-10-21 DOI: 10.1109/ISOCC50952.2020.9333091
Y. A. Tavares, Sewon Lee, Seunghyun Kim, Minjae Lee
{"title":"Calibration of M-Channel Time-Interleaved Analog-to-Digital Converters Based on Curve Fitting","authors":"Y. A. Tavares, Sewon Lee, Seunghyun Kim, Minjae Lee","doi":"10.1109/ISOCC50952.2020.9333091","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333091","url":null,"abstract":"This paper presents a foreground calibration for time-interleaved analog-to-digital converters (TI-ADCs) based on curve fitting for any TI-ADC interleaving order. It outperforms the cited methods by utilizing a hardware efficient digital correction scheme while obtaining an accurate estimation of the channels mismatches. A commercial 12-bit 3.6 GS/s TI-ADC is employed to validate the proposed calibration.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126662691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Booth Fusion: Efficient Bit Fusion Multiplier with Booth Encoding 展台融合:有效的位融合乘数与展台编码
2020 International SoC Design Conference (ISOCC) Pub Date : 2020-10-21 DOI: 10.1109/ISOCC50952.2020.9332943
Seokho Lee, Youngmin Kim
{"title":"Booth Fusion: Efficient Bit Fusion Multiplier with Booth Encoding","authors":"Seokho Lee, Youngmin Kim","doi":"10.1109/ISOCC50952.2020.9332943","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9332943","url":null,"abstract":"Recently, several attempts have been made to optimize Deep Neural Networks (DNNs) through various hardware acceleration methods. Among them, Bit Fusion, the dynamic bit-level fusion/decomposition hardware architecture, was noted. We introduce a new model structure, Booth Fusion, which makes dynamic bit-level operations more efficient by implementing Bit Fusion with booth encoding. Our design shows improvements in 16.4% for the number of LUT and 14.2% for throughput.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128271152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An All-Digital MDLL for Programmable N/M-ratio Frequency Multiplication 用于可编程N/ m比倍频的全数字MDLL
2020 International SoC Design Conference (ISOCC) Pub Date : 2020-10-21 DOI: 10.1109/ISOCC50952.2020.9332935
Taeyeon Kim, Sunguk Choi, S. Han, Jongsun Kim
{"title":"An All-Digital MDLL for Programmable N/M-ratio Frequency Multiplication","authors":"Taeyeon Kim, Sunguk Choi, S. Han, Jongsun Kim","doi":"10.1109/ISOCC50952.2020.9332935","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9332935","url":null,"abstract":"A multiplying delay-locked loop (MDLL)-based all-digital frequency synthesizer for de-skewed N/M-ratio clock frequency synthesis is presented. By eliminating the analog components such as a charge pump, the proposed all-digital frequency synthesizer achieves low sensitivity to device mismatch, resulting in improved jitter characteristics. Fabricated in a 0.13-µm 1.2-V CMOS process, the proposed all-digital MDLL achieves programmable N/M-ratio frequency multiplication, where N = 1~31 and M = 1~15. The proposed MDLL achieves a measured peak-to-peak jitter of about 12 ps at 1 GHz with N/M= 8/1. It occupies an active area of 0.035 mm2, and dissipates 10.3 mW at 1.0 GHz.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134454791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A K-band VCO-based Impulse Generator for UWB Radar Sensors 一种基于k波段vco的超宽带雷达脉冲发生器
2020 International SoC Design Conference (ISOCC) Pub Date : 2020-10-21 DOI: 10.1109/ISOCC50952.2020.9333093
B. Seo, Y. Eo, S. Jung
{"title":"A K-band VCO-based Impulse Generator for UWB Radar Sensors","authors":"B. Seo, Y. Eo, S. Jung","doi":"10.1109/ISOCC50952.2020.9333093","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333093","url":null,"abstract":"A CMOS K-band impulse generator for UWB radar IC is presented. To provide the short UWB impulse signal, a carrier-based impulse generator is employed, which combines the VCO and active RF switch for windowing the LO signal. The tunability of the center frequency and bandwidth are 22.3 - 25.2 GHz and 0.18 - 3 GHz, respectively. The UWB impulse generator is fabricated in a 65 nm CMOS process and consuming 21.3 mW from a single 1.2-V supply.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125600103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Design of 5.8 GHz Ultralow-Power Wake-up Receiver: 14 kHz On Off Keying for DSRC Application 用于DSRC的5.8 GHz超低功耗唤醒接收机:14khz开断键控设计
2020 International SoC Design Conference (ISOCC) Pub Date : 2020-10-21 DOI: 10.1109/ISOCC50952.2020.9332976
S. Choi, Kangyoon Lee
{"title":"A Design of 5.8 GHz Ultralow-Power Wake-up Receiver: 14 kHz On Off Keying for DSRC Application","authors":"S. Choi, Kangyoon Lee","doi":"10.1109/ISOCC50952.2020.9332976","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9332976","url":null,"abstract":"This paper proposes an ultralow-power wake-up receiver(WuRx) for DSRC (Dedicated Short Range Communication) transceiver application. The proposed WuRx receives 5.8 GHz signal and demodulates it into a 14 kHz on off keyed signal. The proposed WuRx is fabricated in 0.13- µm CMOS technology with the size of 0.26 mm2. At the operating frequency of 5.8 GHz, WuR achieves a -62 dBm sensitivity while consuming 3.3 µW from a 0.9 V supply voltage.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115028904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Peak Current Control Boost Converter with Time-Multiplex 峰值电流控制时间复用升压变换器
2020 International SoC Design Conference (ISOCC) Pub Date : 2020-10-21 DOI: 10.1109/ISOCC50952.2020.9332969
Elizabeth Amyouny, Yixuan He, Kyung Ki Kim, Yong-Bin Kim
{"title":"Peak Current Control Boost Converter with Time-Multiplex","authors":"Elizabeth Amyouny, Yixuan He, Kyung Ki Kim, Yong-Bin Kim","doi":"10.1109/ISOCC50952.2020.9332969","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9332969","url":null,"abstract":"A single-inductor dual output boost converter behavioral model was designed using a 180nm CMOS technology and VerilogA. The converter adopts time-multiplexing control by providing independent supply voltages (3.0V and 4.0V) and adjustable peak current for dual output system loads including battery charging. The converter was analyzed and compared to existing architectures presented in literature in the aspects of power path and control scheme. The proposed topology and control loop can be extended to include additional outputs. Implementation of the power stage, controller, and functional blocks are discussed.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115388979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Quadcopters Flight Simulation Considering the Influence of Wind 考虑风影响的四轴飞行器飞行仿真
2020 International SoC Design Conference (ISOCC) Pub Date : 2020-10-21 DOI: 10.1109/ISOCC50952.2020.9333107
M. Ida, Hiroki Nishikawa, Xiangbo Kong, Ittetsu Taniguchi, H. Tomiyama
{"title":"A Quadcopters Flight Simulation Considering the Influence of Wind","authors":"M. Ida, Hiroki Nishikawa, Xiangbo Kong, Ittetsu Taniguchi, H. Tomiyama","doi":"10.1109/ISOCC50952.2020.9333107","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333107","url":null,"abstract":"Quadcopters are widely used in luggage delivery and aerial photography. However, it is difficult to fly quadcopters outdoors freely due to laws such as aviation law. Quadcopters simulation modeling solves this problem, but few studies consider the influence of wind in the simulation. In this work, we construct a program considering the influence of wind and implement the wind on AirSim. The experimental results show that flying time in a simulator using the proposed program is almost the same as the flying time calculated by the formula.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113958224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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