An Energy-Efficient Imprecise Adder with a Lower-part Constant Approximation

Abstract

This paper proposes a novel approximate adder that significantly reduces power and energy consumption by leveraging a lower-part constant scheme. When implemented with a 32-nm CMOS technology, the proposed adder reduces area, power, power-delay product, energy-delay product, and area-delay product, respectively, of 43%, 49%, 76%, 89%, and 73% compared to the ripple carry adder that is a traditional precise adder. Also, we demonstrate that our adder design can remarkably reduce power and energy consumption of digital image processing applications while obtaining an acceptable output image quality.