2020 International SoC Design Conference (ISOCC)最新文献

Extraction of ROM Data from Bitstream in Xilinx FPGA 在Xilinx FPGA中从比特流中提取ROM数据

2020 International SoC Design Conference (ISOCC) Pub Date : 2020-10-21 DOI: 10.1109/ISOCC50952.2020.9333036

Soyeon Choi, Jieun Yeo, Hoyoung Yoo

引用次数: 0

Sequential Compression Using Efficient LUT Correlation for Display Defect Compensation 基于高效LUT相关的序列压缩显示缺陷补偿

2020 International SoC Design Conference (ISOCC) Pub Date : 2020-10-21 DOI: 10.1109/ISOCC50952.2020.9332953

Jooyong Choi, Suk-ju Kang, Minjoo Lee, Jun-Young Park, Jiwoong Lee

引用次数: 0

A Design of 5.8GHz Tunable Band Noise Cancelling CMOS LNA for DSRC Communications 用于DSRC通信的5.8GHz可调谐频段降噪CMOS LNA设计

2020 International SoC Design Conference (ISOCC) Pub Date : 2020-10-21 DOI: 10.1109/ISOCC50952.2020.9332934

Dong Won Lee, Kangyoon Lee

引用次数: 0

A Reconfigurable Approximate Floating-Point Multiplier with kNN 具有kNN的可重构近似浮点乘法器

2020 International SoC Design Conference (ISOCC) Pub Date : 2020-10-21 DOI: 10.1109/ISOCC50952.2020.9332978

Younggyun Cho, Mi Lu

{"title":"A Reconfigurable Approximate Floating-Point Multiplier with kNN","authors":"Younggyun Cho, Mi Lu","doi":"10.1109/ISOCC50952.2020.9332978","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9332978","url":null,"abstract":"Due to the high demands for computing, the available resources always lack. The approximate computing technique is the key to lowering hardware complexity and improving energy efficiency and performance. However, it is a challenge to properly design approximate multipliers since input data are unseen to users. This challenge can be overcome by Machine Learning (ML) classifiers. ML classifiers can predict the detailed feature of upcoming input data. Previous approximate multipliers are designed using simple adders based on ML classifiers but by using a simple adder-based approximate multiplier, the level of approximation cannot change at runtime. To overcome this drawback, using an accumulator and reconfigurable adders instead of simple adders are proposed in this paper. Also, the rounding technique is applied to approximate floating-point multipliers for further improvement. Our experimental results show that when the error tolerance of our target application is less than 5%, the proposed approximate multiplier can save area by 70.98%, and when the error tolerance is less than 3%, a rounding enhanced simple adders-based approximate multiplier can save area by 65.9% and a reconfigurable adder-based approximate multiplier with rounding can reduce the average delay and energy by 54.95% and 46.67% respectively compared to an exact multiplier.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125291767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Fast Prototyping of a Deep Neural Network on an FPGA 基于FPGA的深度神经网络快速原型设计

2020 International SoC Design Conference (ISOCC) Pub Date : 2020-10-21 DOI: 10.1109/ISOCC50952.2020.9333030

Wonjong Kim, Hyegang Jun

引用次数: 1

Effective Software Scheme of the Space Vector Modulation Using One-Chip Micro-Controller 利用单片机实现空间矢量调制的有效软件方案

2020 International SoC Design Conference (ISOCC) Pub Date : 2020-10-21 DOI: 10.1109/ISOCC50952.2020.9333010

W. Choi

引用次数: 0

Compact CNN Training Accelerator with Variable Floating-Point Datapath 紧凑的CNN训练加速器与可变浮点数据路径

2020 International SoC Design Conference (ISOCC) Pub Date : 2020-10-21 DOI: 10.1109/ISOCC50952.2020.9332986

Jiun Hong, TaeGeon Lee, Saad Arslan, Hyungwon Kim

引用次数: 1

50 MHz 3-Level Buck Converter with added Boost Converter 50兆赫3级降压转换器与增加升压转换器

2020 International SoC Design Conference (ISOCC) Pub Date : 2020-10-21 DOI: 10.1109/ISOCC50952.2020.9333088

S. SunitaM., D. MayurG., Preet Bedi, Nagesh Verma, Shashidhar Tantry

引用次数: 0

A Two-stage Training Mechanism for the CNN with Trainable Activation Function 具有可训练激活函数的CNN的两阶段训练机制

2020 International SoC Design Conference (ISOCC) Pub Date : 2020-10-21 DOI: 10.1109/ISOCC50952.2020.9333116

K. Chen, Jing-Wen Liang

{"title":"A Two-stage Training Mechanism for the CNN with Trainable Activation Function","authors":"K. Chen, Jing-Wen Liang","doi":"10.1109/ISOCC50952.2020.9333116","DOIUrl":"https://doi.org/10.1109/ISOCC50952.2020.9333116","url":null,"abstract":"Activation function design is critical in the convolutional neural network (CNN) because it affects the learning speed and the precision of classification. In a hardware implementation, using traditional activation function may cause large hardware area overhead due to its complicated calculation such as exponential. To reduce the hardware overhead, Taylor series expansion is a popular way to approximate the traditional activation function. However, this approach brings some approximation errors, which reduce the accuracy of the involved CNN model. Therefore, the trainable activation function and a two-stage training mechanism are proposed in this paper to compensate for the accuracy loss due to the Taylor series expansion. After initializing the involved trainable activation function, the coefficients of the trainable activation function according to different neural network layer will be adjusted properly along with the neural network training process. Compared with the conventional approach, the proposed trainable activation function can involve fewer Taylor expansion terms to improve the classification accuracy by 2.24% to 53.96%. Therefore, CNN with trainable activation functions can achieve better classification accuracy with less area cost.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129565592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Implementation of a Round Robin Processing Element for Deep Learning Accelerator

2020 International SoC Design Conference (ISOCC) Pub Date : 2020-10-21 DOI: 10.1109/ISOCC50952.2020.9333012

Eunchong Lee, Yongseok Lee, Sang-Seol Lee, Byoung-Ho Choi

引用次数: 1