50兆赫3级降压转换器与增加升压转换器

2020 International SoC Design Conference (ISOCC) Pub Date : 2020-10-21 DOI:10.1109/ISOCC50952.2020.9333088

S. SunitaM., D. MayurG., Preet Bedi, Nagesh Verma, Shashidhar Tantry

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引用次数: 0

摘要

本文介绍了一个50MHz, 3.5V输入，0.6- 3.12V输出，3电平降压转换器，包括一个校准电路，以确保在飞行电容器上的恒定电压。此外，升压转换器的设计将最大输出电压水平提高到5.8V。所有电路及其模块在Cadence virtuoso上采用45nm CMOS技术进行设计和仿真。观察到3电平降压变换器的峰值效率为90.3%，改进升压变换器的峰值效率为93.6%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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50 MHz 3-Level Buck Converter with added Boost Converter

This paper presents a 50MHz, 3.5V input and 0.6- 3.12V output, 3-Level Buck Converter with the inclusion of a calibration circuit to ensure a constant voltage across the flying capacitor. Additionally, a Boost Converter is designed to increase the max output voltage level to 5.8V. All the circuits and their blocks are designed and simulated in 45nm CMOS technology on Cadence virtuoso. Peak efficiency is observed to be 90.3% for 3-Level Buck Converter and 93.6% for the modified Boost Converter.

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2020 International SoC Design Conference (ISOCC)

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