用于DSRC通信的5.8GHz可调谐频段降噪CMOS LNA设计

2020 International SoC Design Conference (ISOCC) Pub Date : 2020-10-21 DOI:10.1109/ISOCC50952.2020.9332934

Dong Won Lee, Kangyoon Lee

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引用次数: 0

摘要

本文介绍了用于DSRC通信的5.8GHz降噪CMOS LNA。LNA设计为差分输出，采用平衡结构和电阻反馈降噪技术。可调谐负载电容器组实现宽带输入匹配和增益选择。该LNA采用130nm CMOS技术实现，在中心频率处仿真增益24.2dB, PldB为-13.46dB，噪声系数(NF)为2.74dB。1.2V供电时的功耗为10.51mW。芯片面积为509×559µm2

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A Design of 5.8GHz Tunable Band Noise Cancelling CMOS LNA for DSRC Communications

This article presents about 5.8GHz noise cancelling CMOS LNA for DSRC communication. The LNA is designed with differential output with balun architecture and resistive-feedback noise cancelling technique. Tunable load capacitor bank achieves wideband input matching and gain selection. The LNA is implemented in 130nm CMOS technology and achieves a simulated gain of 24.2dB and PldB of -13.46dB and noise figure(NF) of 2.74dB at center frequency. The power consumption is 10.51mW at 1.2V power supply. The chip area is 509×559µm2

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2020 International SoC Design Conference (ISOCC)

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