A Voting Phase Detector Design with Mitigated Process Variation

Abstract

A Phase Detector is an indispensable component in a Delay-Locked Loop (DLL). It compares the phases of two input clock signals and then produce a binary lead/lag signal to indicate which clock signal arrives earlier. The resolution of a PD often determines the accuracy of a DLL in terms of the phase error. Unfortunately, a traditional cell-based PD is strongly susceptible to the process variation. In this paper, we propose a “Voting PD design” to alleviate this problem. First, a number of primitive phase detectors are incorporated, and then their primitive results undergo a majority voting process to produce the final lead/lag signal, and thereby enhancing the overall resolution. A statistical approximation shows that process variation can be compressed to 53% using a voting group of 5 primitive phase detectors.