An All-Digital MDLL for Programmable N/M-ratio Frequency Multiplication

A multiplying delay-locked loop (MDLL)-based all-digital frequency synthesizer for de-skewed N/M-ratio clock frequency synthesis is presented. By eliminating the analog components such as a charge pump, the proposed all-digital frequency synthesizer achieves low sensitivity to device mismatch, resulting in improved jitter characteristics. Fabricated in a 0.13-µm 1.2-V CMOS process, the proposed all-digital MDLL achieves programmable N/M-ratio frequency multiplication, where N = 1~31 and M = 1~15. The proposed MDLL achieves a measured peak-to-peak jitter of about 12 ps at 1 GHz with N/M= 8/1. It occupies an active area of 0.035 mm2, and dissipates 10.3 mW at 1.0 GHz.