Improving Analysis Coverage for Dynamic IR Drop Sign-off in FinFET SoC Design

Abstract

Power grid design is one of the key challenges in large SoC design. In order to guarantee robustness of the power grid, dynamic IR drop should be analyzed correctly. In this paper, we have described weakness of vectorless analysis and necessity of vector-based analysis. We have improved analysis coverage for the more accurate dynamic IR drop analysis. The analysis results were obtained with the FinFET technology node and all simulations were done in the ANSYS RedHawk.