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2010 IEEE Radio Frequency Integrated Circuits Symposium最新文献

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A stage-scaled distributed power amplifier achieving 110GHz bandwidth and 17.5dBm peak output power 实现110GHz带宽和17.5dBm峰值输出功率的级尺分布式功率放大器
2010 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2010-05-23 DOI: 10.1109/RFIC.2010.5477261
Jiashu Chen, A. Niknejad
{"title":"A stage-scaled distributed power amplifier achieving 110GHz bandwidth and 17.5dBm peak output power","authors":"Jiashu Chen, A. Niknejad","doi":"10.1109/RFIC.2010.5477261","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477261","url":null,"abstract":"This paper presents the design of a pseudo-differential distributed power amplifier in a 0.13µm SiGe BiCMOS process. Based on the newly proposed efficiency enhancing stage-scaling technique, the distributed power amplifier achieves a small-signal bandwidth of 110GHz, a peak saturated output power of 17.5dBm and a peak PAE of 13.2%. The measured 3dB output power bandwidth is greater than 77GHz. The amplifier consumes 119mA from a 3V supply.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116304050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A 6fJ/step, 5.5ps time-to-digital converter for a digital PLL in 40nm digital LP CMOS 用于40nm数字LP CMOS数字锁相环的6fJ/step, 5.5ps时间-数字转换器
2010 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2010-05-23 DOI: 10.1109/RFIC.2010.5477312
J. Borremans, K. Vengattarmane, J. Craninckx
{"title":"A 6fJ/step, 5.5ps time-to-digital converter for a digital PLL in 40nm digital LP CMOS","authors":"J. Borremans, K. Vengattarmane, J. Craninckx","doi":"10.1109/RFIC.2010.5477312","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477312","url":null,"abstract":"A compact (0.01mm2) coarse-fine time-to-digital converter (TDC) in 40nm LP CMOS achieves 5.5ps resolution using parallel delay lines. A 6fJ/conversion step efficiency is achieved thanks to efficient residue calculation. A 0.8LSB single-shot precision and low DNL are reached thanks to simple calibration which is possible in fractional-N PLLs. Further, metastability avoidance and digital error correction are implemented. This 14-bit architecture operates at a 40MS/s reference clock.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125923428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
High-efficiency reconfigurable RF transmitter for wireless sensor network applications 用于无线传感器网络应用的高效可重构射频发射机
2010 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2010-05-23 DOI: 10.1109/RFIC.2010.5477266
F. Carrara, G. Palmisano
{"title":"High-efficiency reconfigurable RF transmitter for wireless sensor network applications","authors":"F. Carrara, G. Palmisano","doi":"10.1109/RFIC.2010.5477266","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477266","url":null,"abstract":"In this paper, a 90-nm CMOS 1.2-V ultra-low-power RF transmitter for wireless sensor networks is presented. A wideband topology guarantees continuous frequency coverage from 300 to 960 MHz, thus enabling easy reconfigurability through the most popular sub-GHz bands. At 300 MHz (960 MHz), the transmitter is able to deliver a 10.2-dBm (10.3-dBm) output power with 63% (46%) system efficiency. The proposed circuit features extensive use of dynamic current biasing for improved efficiency in back-off. Substantial power saving in excess of 80% are achieved compared to constant bias operation. Linear operation with variable-envelope input is also demonstrated, since the transmitter exhibits a 8.5-dBm output power, 37% efficiency, and −30-dBc adjacent channel power ratio with π/4-DQPSK 200-ksps input excitation.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129709007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 0.13-µm CMOS wireless reflector for phase sweep cooperative diversity 一种用于相位扫描协同分集的0.13 μ m CMOS无线反射器
2010 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2010-05-23 DOI: 10.1109/RFIC.2010.5477396
Jean-François Bousquet, S. Magierowski, G. Messier, Zhixing Zhao
{"title":"A 0.13-µm CMOS wireless reflector for phase sweep cooperative diversity","authors":"Jean-François Bousquet, S. Magierowski, G. Messier, Zhixing Zhao","doi":"10.1109/RFIC.2010.5477396","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477396","url":null,"abstract":"A 4-GHz 1.2-V all-analog wireless reflector acting as a cooperative diversity repeater is built in 0.13-μm CMOS technology. Interfaced with a dipole antenna, the circuit achieves 22.3-dB gain for a low power consumption equal to 120 μW. By applying slow phase sweeping at the reflector node, diversity gain is achieved and the coverage area of an indoor wireless network is increased by a factor of 2.5.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128588061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
2-4 and 9-12 Gb/s CMOS fully integrated ILO-based CDR 2-4和9-12 Gb/s CMOS完全集成基于ilo的CDR
2010 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2010-05-23 DOI: 10.1109/RFIC.2010.5477391
O. Mazouffre, R. Toupe, M. Pignol, Y. Deval, J. Bégueret
{"title":"2-4 and 9-12 Gb/s CMOS fully integrated ILO-based CDR","authors":"O. Mazouffre, R. Toupe, M. Pignol, Y. Deval, J. Bégueret","doi":"10.1109/RFIC.2010.5477391","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477391","url":null,"abstract":"A CDR dedicated to satellite data link is presented. The clock recovery function is made-up of an Injection Locked Oscillator combined with an analog phase alignment circuit. The circuit covers two bit-rate ranges: 2.2 to 4.3 Gb/s and 9.1 to 12.1 Gb/s. It was designed in 130 nm CMOS bulk process from STMicroelectronics. The overall power dissipation is 400 mW in the first bit-rate range and 480 mW in the second including 220 mW for I/O buffers. The eye opening at 10-9 of bit error rate is 940 mUI/440 mV at 3.1 Gb/s and 720 mUI/300 mV at 10.3 Gb/s.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128905942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
900MHz/1800MHz GSM base station LNA with sub-1dB noise figure and +36dBm OIP3 900MHz/1800MHz GSM基站LNA，噪声系数低于1db, OIP3 +36dBm
2010 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2010-05-23 DOI: 10.1109/RFIC.2010.5477321
D. Leenaerts, J. Bergervoet, J. Lobeek, M. Schmidt-Szalowski
{"title":"900MHz/1800MHz GSM base station LNA with sub-1dB noise figure and +36dBm OIP3","authors":"D. Leenaerts, J. Bergervoet, J. Lobeek, M. Schmidt-Szalowski","doi":"10.1109/RFIC.2010.5477321","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477321","url":null,"abstract":"A sub-1dB NF fully integrated low noise amplifier in a 0.25µm SiGe∶C BiCMOS technology targeting GSM base-station applications will be discussed. The two-stage LNA is housed in a HVSON10 package and mounted on a PCB. The LNA measures a NF of 0.75dB in the 900MHz band and 0.9dB in the 1800MHz band. The LNA is matched to 50Ω at the RF I/O pins of the IC and has integrated ESD protection on all IC pins. The LNA achieves an OIP3 of +36dBm, a 1-dB OCP of +19dBm while dissipating 190mW. The LNA performance is in line with the compound technology LNA counterparts.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132487213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Co-design considerations for frequency drift compensation in BAW-based time reference application 基于baw的时间参考应用中频率漂移补偿的协同设计考虑
2010 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2010-05-23 DOI: 10.1109/RFIC.2010.5477303
S. Razafimandimby, D. Petit, P. Bar, S. Joblot, J. Carpentier, J. Morelle, C. Arnaud1, G. Parat, P. Garcia, C. Garnier
{"title":"Co-design considerations for frequency drift compensation in BAW-based time reference application","authors":"S. Razafimandimby, D. Petit, P. Bar, S. Joblot, J. Carpentier, J. Morelle, C. Arnaud1, G. Parat, P. Garcia, C. Garnier","doi":"10.1109/RFIC.2010.5477303","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477303","url":null,"abstract":"In order to take up the challenge of BAW-based time reference, this paper presents new BAW/Integrated Circuits (IC) co-integration considerations. For the demonstration, a SiP approach is proposed where the Solidly Mounted Resonator (SMR) has been directly flip-chipped on the top of the IC. This 2.5GHz oscillator reaches a −93dBc/Hz phase noise at a 2kHz carrier offset for a 7.3mW power consumption. A 5bit switched capacitor bank permits to correct process deviations with a 12.5kHz accuracy while a varactor capacitance allows compensating a SMR with a −4.2ppm/°C Temperature Coefficient of Frequency (TCF) in a [−40°C,85°C] temperature range.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"6 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131672484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A CMOS transceiver with internal PA and digital pre-distortion for WLAN 802.11a/b/g/n Applications 内置PA和数字预失真的CMOS收发器，适用于WLAN 802.11a/b/g/n应用
2010 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2010-05-23 DOI: 10.1109/RFIC.2010.5477394
Chia-Jun Chang, Po-Chih Wang, Chih-Yu Tsai, Chin-Lung Li, Chiao-Ling Chang, Han-Jung Shih, M. Tsai, Wen-Shan Wang, Ka-Un Chan, Ying-Hsi Lin
{"title":"A CMOS transceiver with internal PA and digital pre-distortion for WLAN 802.11a/b/g/n Applications","authors":"Chia-Jun Chang, Po-Chih Wang, Chih-Yu Tsai, Chin-Lung Li, Chiao-Ling Chang, Han-Jung Shih, M. Tsai, Wen-Shan Wang, Ka-Un Chan, Ying-Hsi Lin","doi":"10.1109/RFIC.2010.5477394","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477394","url":null,"abstract":"A 2.4/5GHz Fully-Integrated Transceiver is implemented in 65nm CMOS technology. To alleviate the cost of external front-end components, the G-mode RF transmit/receive (T/R) switch and a power-efficient linear CMOS PA are fully integrated on-chip. On the other hand, for better performance, only the A-mode PA is integrated on-chip while the external T/R switch is used. It shows 5dB and 5.5dB NF in the G-mode and A-mode receivers respectively. Also, the transmitter delivers an average power of 18dBm OFDM (64QAM, 54MBPS) signal with EVM of -28dB for G-mode application and 16dBm OFDM (64QAM, 54MBPS) signal with EVM of −28dB for A-mode application after digital pre-distortion.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"615 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123340500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
A 6GHz direct digital synthesizer MMIC with nonlinear DAC and wave correction ROM 带有非线性DAC和波校正ROM的6GHz直接数字合成器MMIC
2010 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2010-05-23 DOI: 10.1109/RFIC.2010.5477279
Danyu Wu, Gaopeng Chen, Jianwu Chen, Xinyu Liu, Li-Xin Zhao, Zhi Jin
{"title":"A 6GHz direct digital synthesizer MMIC with nonlinear DAC and wave correction ROM","authors":"Danyu Wu, Gaopeng Chen, Jianwu Chen, Xinyu Liu, Li-Xin Zhao, Zhi Jin","doi":"10.1109/RFIC.2010.5477279","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477279","url":null,"abstract":"This paper proposes a new DDS architecture combined with Nonlinear DAC and Wave-Correction-ROM (WCR) which shows both high operating speed and accuracy. Based on this architecture, a 6GHz 8-bit DDS MMIC is designed and fabricated in 60GHz GaAs HBT Technology. The DDS MMIC includes 8-bit pipeline accumulator, an 8×8×3bits WCR, two combined DACs and an analog Gilbert Cell for sine-wave generation with 8-bit amplitude resolution. The DDS chip is tested in on-wafer measurement system. The measured spurious free dynamic range (SFDR) is 33.96dBc with 2.367GHz output under a 6GHz maximum clock (FCW=0×65). It shows an average SFDR of 37.5dBc and the worst case SFDR of 31.4dBc (FCW=0×70) within the whole Nyquist band under a 5GHz clock frequency. The whole chip occupies 2.4×2mm2 of area consuming 3.27W of power from a single −4.6Vpower supply.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125925540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A low power LNA using miniature 3D inductor without area penalty of passive components 采用无源元件面积损失的微型3D电感的低功耗LNA
2010 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2010-05-23 DOI: 10.1109/RFIC.2010.5477252
A. Tanabe, K. Hijioka, H. Nagase, Y. Hayashi
{"title":"A low power LNA using miniature 3D inductor without area penalty of passive components","authors":"A. Tanabe, K. Hijioka, H. Nagase, Y. Hayashi","doi":"10.1109/RFIC.2010.5477252","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477252","url":null,"abstract":"A low power 5GHz LNA without area penalty of inductors has been fabricated. Because of a miniature 3D vertical solenoid inductor, a chip area of this LNA is as small as that of feedback type LNAs which do not need passive components. A noise and a power consumption are smaller than those LNAs. Because of a small parasitic capacitance of the 3D inductor and a controlled series resistance considering skin and proximity effects, a 15.7dB power gain and a 2.0dB noise factor at 5GHz have been achieved with only 3.6mW power consumption. This LNA with the miniature 3D solenoid inductor is preferable for low power and low cost RF/mixed-signal SoCs.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123757623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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