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2010 IEEE Radio Frequency Integrated Circuits Symposium最新文献

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A wide-range VCO with optimum temperature adaptive tuning 具有最佳温度自适应调谐的宽量程压控振荡器
2010 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2010-05-23 DOI: 10.1109/RFIC.2010.5477264
B. Saeidi, Joshua Cho, G. Taskov, A. Paff
{"title":"A wide-range VCO with optimum temperature adaptive tuning","authors":"B. Saeidi, Joshua Cho, G. Taskov, A. Paff","doi":"10.1109/RFIC.2010.5477264","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477264","url":null,"abstract":"This paper presents an integrated wide-range VCO with a modified tuning scheme to deal with VCO frequency drift over temperature. In this approach, during the coarse-tune operation, VCO tune voltage is a function of temperature such that it resembles the inverse function of VCO fine-tune characteristic. Without degrading VCO performance, the proposed temperature adaptive tuning optimizes the maximum tolerable VCO temperature frequency drift over which PLL remains locked. As a result, VCO gain can be reduced significantly, making VCO less sensitive to PLL tune voltage noise. Integrated in a multi-standard multi-band transceiver with a small VCO gain of 50MHz/V at 3.90GHz, PLL remains locked despite 45MHz frequency drift of VCO over [−30°C, 85°C]. Using an on-chip inductor, VCO covers from 3.15GHz to 4.60GHz, achieving −138.0dBc/Hz phase noise at 3.0MHz at 3.90GHz by drawing just 8.5mA from 1.60V supply in 0.13u CMOS process.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125167955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Single-chip WiFi b/g/n 1×2 SoC with fully integrated front-end & PMU in 90nm digital CMOS technology 单芯片WiFi b/g/n 1×2 SoC具有完全集成的前端和PMU，采用90nm数字CMOS技术
2010 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2010-05-23 DOI: 10.1109/RFIC.2010.5477372
J. Jensen, R. Sadhwani, A. Kidwai, B. Jann, A. Oster, M. Sharkansky, I. Ben-bassat, O. Degani, S. Porat, A. Fridman, H. Shang, C. Chu, A. Ly, M. Smith
{"title":"Single-chip WiFi b/g/n 1×2 SoC with fully integrated front-end & PMU in 90nm digital CMOS technology","authors":"J. Jensen, R. Sadhwani, A. Kidwai, B. Jann, A. Oster, M. Sharkansky, I. Ben-bassat, O. Degani, S. Porat, A. Fridman, H. Shang, C. Chu, A. Ly, M. Smith","doi":"10.1109/RFIC.2010.5477372","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477372","url":null,"abstract":"We report a compact 802.11b/g/n MIMO SoC with fully integrated transceiver, on-chip PMU including dc-dc converters, PHY, MAC, PCIe and a non-volatile memory. The transceiver includes on-chip PA, LNA and T/R switch. Fabricated in 90nm standard digital CMOS technology, this IC consumes 663/878mW (Rx/Tx 54Mbps) with an area of approx 33mm2. A peak saturated power of 24dBm is achieved at antenna.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125111651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 228µW injection locked ring oscillator based BPSK demodulator in 65nm CMOS 基于228µW注入锁环振荡器的65nm CMOS BPSK解调器
2010 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2010-05-23 DOI: 10.1109/RFIC.2010.5477316
Qiang Zhu, Yang Xu
{"title":"A 228µW injection locked ring oscillator based BPSK demodulator in 65nm CMOS","authors":"Qiang Zhu, Yang Xu","doi":"10.1109/RFIC.2010.5477316","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477316","url":null,"abstract":"This paper presents an ultra-low power BPSK demodulator based on injection locked oscillators (ILOs). Two second harmonic ILOs are employed to convert BPSK signals to ASK signals which are demodulated by an envelope detector to baseband signals. For sub-GHz applications, the ILOs are implemented using ring oscillators to allow compact chip area and ultra-low power dissipation. The prototype demodulator is fabricated in a 65nm CMOS technology that consumes 228µW of power and occupies 0.014mm2 of die area. Measurement results reveal the demodulation of BPSK signal at 750–900MHz carrier with the minimum sensitivity of −33dBm.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114578992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A layout efficient, vertically stacked, resonator-coupled bandpass filter in LTCC for 60 GHz SOP transceivers 用于60ghz SOP收发器的高效布局、垂直堆叠、LTCC谐振耦合带通滤波器
2010 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2010-05-23 DOI: 10.1109/RFIC.2010.5477319
R. Amaya
{"title":"A layout efficient, vertically stacked, resonator-coupled bandpass filter in LTCC for 60 GHz SOP transceivers","authors":"R. Amaya","doi":"10.1109/RFIC.2010.5477319","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477319","url":null,"abstract":"This paper describes the design and implementation of a layout efficient bandpass filter implemented in Low-Temperature Co-fired Ceramic (LTCC) substrates. Applications for this filter include band select filters for 60 GHz System-On-Package transceivers. Two bandpass filters based on a quasi-elliptic configuration were implemented here using four half-wavelength resonators. The first filter uses all planar resonators to achieved a measured insertion loss of 3.7 dB and a return loss ≫ 10 dB and with a layout area of 1.263mm2. The second filter uses vertical stacking of two of its resonators to reduce the layout area and achieved higher immunity to process variations. Measurements for the second filter show an IL of 3.4 dB while maintaining a RL ≫ 10 dB. The vertically stacked filter consumes a layout area of 0.811mm2, corresponding to a layout reduction of 36% compared to the planar filter with performance less prone for process variations.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115881080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Cellular antenna switches for multimode applications based on a Silicon-on-Insulator technology 基于绝缘体上硅技术的多模应用蜂窝天线开关
2010 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2010-05-23 DOI: 10.1109/RFIC.2010.5477354
A. Tombak, C. Iversen, Jean-Blaise Pierres, D. Kerr, M. Carroll, P. Mason, E. Spears, T. Gillenwater
{"title":"Cellular antenna switches for multimode applications based on a Silicon-on-Insulator technology","authors":"A. Tombak, C. Iversen, Jean-Blaise Pierres, D. Kerr, M. Carroll, P. Mason, E. Spears, T. Gillenwater","doi":"10.1109/RFIC.2010.5477354","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477354","url":null,"abstract":"A Silicon-on-Insulator (SOI) CMOS technology on high resistivity silicon substrates is presented for the design of cellular antenna switches. The design and measurement results for an SP9T cellular antenna switch based on this technology are presented. To the best of our knowledge, this is the first demonstration of an SP9T cellular antenna switch with adequate intermodulation and harmonic distortion performance on a high resistivity SOI CMOS technology.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115927865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
A CMOS Ultra-wideband radar transmitter with pulsed oscillator 一种带脉冲振荡器的CMOS超宽带雷达发射机
2010 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2010-05-23 DOI: 10.1109/RFIC.2010.5477389
Sungeun Lee, Sanghoon Sim, Songcheol Hong
{"title":"A CMOS Ultra-wideband radar transmitter with pulsed oscillator","authors":"Sungeun Lee, Sanghoon Sim, Songcheol Hong","doi":"10.1109/RFIC.2010.5477389","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477389","url":null,"abstract":"A design of Ultra-wideband (UWB) radar transmitter is presented. The transmitter which uses a pulsed oscillator consists of pulse generator, switching buffers and control signal generator. The control signal generator includes modulators of binary-phase shift keying (BPSK) and pulse position modulation (PPM) for spreading the spectral lines. It is fabricated using 0.13 µm CMOS technology and the chip size is 910 × 485 µm2. The output spectrum is centered at the 22.0 GHz with the 10-dB bandwidth of 2.48 GHz and the pulse width of output pulse is tunable from 630ps to 830ps. Also, the BPSK and PPM modulations are confirmed. In conclusion, the generated pulse complies with FCC's spectral mask.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124122987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Controlled dither in 90 nm digital to time conversion based direct digital synthesizer for spur mitigation 基于90 nm数字时间转换的直接数字合成器中的抖动控制
2010 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2010-05-23 DOI: 10.1109/RFIC.2010.5477259
S. Talwalkar, T. Gradishar, B. Stengel, G. Cafaro, G. Nagaraj
{"title":"Controlled dither in 90 nm digital to time conversion based direct digital synthesizer for spur mitigation","authors":"S. Talwalkar, T. Gradishar, B. Stengel, G. Cafaro, G. Nagaraj","doi":"10.1109/RFIC.2010.5477259","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477259","url":null,"abstract":"Dithering is used in many discrete to continuous value conversion functions to provide an effective fractional value. This paper reviews the application of dither to a digital-to-time converter (DTC) based digital synthesizer suitable for many common wireless communication systems. Measurements of a 90 nm CMOS implementation using a 5 bit DTC show extension to effective 8 bits.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130027818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A self-healing 2.4GHz LNA with on-chip S11/S21 measurement/calibration for in-situ PVT compensation 带有片上S11/S21测量/校准的自修复2.4GHz LNA，用于原位PVT补偿
2010 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2010-05-23 DOI: 10.1109/RFIC.2010.5477307
Karthik Jayaraman, Q. Khan, B. Chi, Will Beattie, Zhihua Wang, P. Chiang
{"title":"A self-healing 2.4GHz LNA with on-chip S11/S21 measurement/calibration for in-situ PVT compensation","authors":"Karthik Jayaraman, Q. Khan, B. Chi, Will Beattie, Zhihua Wang, P. Chiang","doi":"10.1109/RFIC.2010.5477307","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477307","url":null,"abstract":"This paper presents a 2.4GHz, reconfigurable RF LNA using on-chip peak detection and calibration to measure and optimize its input impedance (S11) and gain (S21) in-situ, compensating for the unpredictable effects of process, voltage and temperature (PVT) variations. Measurement results show that the calibration of the LNA across PVT corners improves the S11 by 5.1dB, S21 by 3dB, while not significantly degrading the Noise Figure (0.22dB degradation) and linearity (1.7dBm degradation).","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122518427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 48
A cost-competitive high performance Junction-FET (JFET) in CMOS process for RF & analog applications 一种具有成本竞争力的高性能CMOS结场效应管(JFET)，适用于射频和模拟应用
2010 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2010-05-23 DOI: 10.1109/RFIC.2010.5477348
Yun Shi, R. Rassel, R. Phelps, P. Candra, D. Hershberger, X. Tian, S. Sweeney, J. Rascoe, B. Rainey, J. Dunn, D. Harame
{"title":"A cost-competitive high performance Junction-FET (JFET) in CMOS process for RF & analog applications","authors":"Yun Shi, R. Rassel, R. Phelps, P. Candra, D. Hershberger, X. Tian, S. Sweeney, J. Rascoe, B. Rainey, J. Dunn, D. Harame","doi":"10.1109/RFIC.2010.5477348","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477348","url":null,"abstract":"in this paper, we present a cost-effective JFET integrated in 0.18µm RFCMOS process. The design is highly compatible with standard CMOS process, therefore can be easily scaled and implemented in advanced technology nodes. The design impact on Ron and Voff is further discussed, providing the insights and guidelines for JFET optimization. Besides the superior flicker noise (1/f noise) characteristics, this JFET device also demonstrates promising RF characteristics such as maximum frequency, linearity, power handling capability, power-added efficiency, indicating a good candidate for RF designs.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127925721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A CMOS wide-bandwidth high-power linear-in-dB variable attenuator using body voltage distribution method 一种采用体电压分布法的CMOS宽带宽大功率db线性可变衰减器
2010 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2010-05-23 DOI: 10.1109/RFIC.2010.5477366
Yan-Yu Huang, W. Woo, Chang-Ho Lee, J. Laskar
{"title":"A CMOS wide-bandwidth high-power linear-in-dB variable attenuator using body voltage distribution method","authors":"Yan-Yu Huang, W. Woo, Chang-Ho Lee, J. Laskar","doi":"10.1109/RFIC.2010.5477366","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477366","url":null,"abstract":"A wide bandwidth, highly linear variable attenuator designed in 0.18µm triple-well CMOS process is presented. This attenuator is based on three cascade π-networks with body voltage distribution scheme to minimize the effects of the input power levels. Measurements show it achieves minimum 1-dB gain compression of 7.5 dBm. The mid-band insertion loss is 1.6 dB and the maximum attenuation is 34.8 dB. This attenuator has a linear-in-dB controllability from 400 MHz to 3.7 GHz with input return loss better than 9 dB. To our knowledge, this is the highest linear CMOS variable attenuator with a wide bandwidth of 3.3 GHz.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130531708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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