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A 68-82 GHz integrated wideband linear receiver using 0.18 µm SiGe BiCMOS 采用0.18µm SiGe BiCMOS的68-82 GHz集成宽带线性接收机
2010 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2010-05-23 DOI: 10.1109/RFIC.2010.5477281
Austin Chen, Y. Baeyens, Young-Kai Chen, Jenshan Lin
{"title":"A 68-82 GHz integrated wideband linear receiver using 0.18 µm SiGe BiCMOS","authors":"Austin Chen, Y. Baeyens, Young-Kai Chen, Jenshan Lin","doi":"10.1109/RFIC.2010.5477281","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477281","url":null,"abstract":"This paper presents a highly integrated wideband linear receiver with on-chip active frequency doubler implemented in a low-cost 200/180 GHz fT/fmax 0.18 µm SiGe BiCMOS technology. Individual receiver circuit blocks including low-noise amplifier, passive balun, mixer, and frequency doubler have been independently characterized and optimized for wideband, NF, and linearity performance. The receiver highlights a 3 dB RF bandwidth of larger than 14 GHz from 68 GHz to at least 82 GHz. The measured peak power conversion gain is 28.1 dB with an input 1 dB compression point of −23.6 dBm, and NF of 8 dB at 77 GHz. Noise figures of 8–10 dB are achieved over the 3 dB bandwidth. The overall chip size is 1350 × 990 µm2 and the total power consumption is 413 mW. To the best of authors' knowledge, this receiver reports the highest 3 dB RF bandwidth with excellent linearity performance among all the prior arts in SiGe HBT/BiCMOS technologies to date.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116613970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A SAW-less CMOS TX for EGPRS and WCDMA 用于EGPRS和WCDMA的无锯CMOS TX
2010 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2010-05-23 DOI: 10.1109/RFIC.2010.5477357
Kurt Hausmann, J. Ganger, Mark Kirschenmann, G. Norris, W. Shepherd, V. Bhan, D. Schwartz
{"title":"A SAW-less CMOS TX for EGPRS and WCDMA","authors":"Kurt Hausmann, J. Ganger, Mark Kirschenmann, G. Norris, W. Shepherd, V. Bhan, D. Schwartz","doi":"10.1109/RFIC.2010.5477357","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477357","url":null,"abstract":"A 90 nm CMOS TX path architected for operation without inter-stage SAW filters is shown. The SAW elimination strategy is purely low noise design but the architecture still achieves DG.09 weighted TX current drain of 50 mA from the battery. The combination of a passive interleaved switching mixer plus digital gain control allows 2% EVM at 2 dbm and 4.2% at −78 dbm.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131407108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A novel low-profile low-parasitic RF package using high-density build-up technology 采用高密度堆积技术的新型低轮廓低寄生射频封装
2010 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2010-05-23 DOI: 10.1109/RFIC.2010.5477358
Chien-Cheng Wei, M. Lin, Chin-Ta Fan, Ta-Hsiang Chiang, Ming-Kuen Chiu, S. Ru, Nan Ni, A. Cardona
{"title":"A novel low-profile low-parasitic RF package using high-density build-up technology","authors":"Chien-Cheng Wei, M. Lin, Chin-Ta Fan, Ta-Hsiang Chiang, Ming-Kuen Chiu, S. Ru, Nan Ni, A. Cardona","doi":"10.1109/RFIC.2010.5477358","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477358","url":null,"abstract":"This paper presents a low-profile low-parasitic RF package by using the high-density build-up (HD-BU) technology. This package achieves much thinner, fine pitch, and exposed design pattern feature for outstanding electrical and thermal performance. The packaging fabrication is simple and only needs several processes. This HD-BU package provides lower parasitic than other lead-frame types due to the use of very thin bonding pads. Additionally, a capacitor chip is assembled using the proposed technology for packaging demonstration and electrical performance evaluation. Based on the experimental results, the measured capacitances at 1-GHz are quite similar before and after packaging. It indicates that the HD-BU package has low parasitic capacitance even at high-frequency operation, and does not affect the electrical performance for the packaged chip. Therefore, these packages are good candidates for applications requiring low profile, low parasitic and low cost.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132725365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 90µW MICS/ISM band transmitter with 22% global efficiency 90µW MICS/ISM波段发射机，全球效率22%
2010 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2010-05-23 DOI: 10.1109/RFIC.2010.5477395
J. Pandey, B. Otis
{"title":"A 90µW MICS/ISM band transmitter with 22% global efficiency","authors":"J. Pandey, B. Otis","doi":"10.1109/RFIC.2010.5477395","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477395","url":null,"abstract":"For fully autonomous implantable or body-worn devices running on harvested energy, the peak and average power dissipation of the radio transmitter must be minimized. We propose a highly integrated 90 µW 400MHz MICS band transmitter with an output power of 20 µW leading to a 22% global efficiency — the highest reported to date for such systems. We introduce a new transmitter architecture based on cascaded multi-phase injection locking and frequency multiplication to enable low power operation and high global efficiency. Our architecture eliminates slow phase/delay-locked loops for frequency synthesis and uses injection locking to achieve a settling time ≪ 250 ns permitting very aggressive duty cycling of the transmitter to conserve energy. At a data-rate of 200 kbps, the transmitter achieves an energy efficiency of 450 pJ/bit. Our 400MHz local oscillator topology demonstrates a figure-of-merit of 204 dB.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132877804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
94 GHz silicon co-integrated LNA and Antenna in a mm-wave dedicated BiCMOS technology 94 GHz硅协集成LNA和天线在毫米波专用BiCMOS技术
2010 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2010-05-23 DOI: 10.1109/RFIC.2010.5477390
R. Pilard, D. Gloria, F. Gianesello, F. Le Pennec, C. Person
{"title":"94 GHz silicon co-integrated LNA and Antenna in a mm-wave dedicated BiCMOS technology","authors":"R. Pilard, D. Gloria, F. Gianesello, F. Le Pennec, C. Person","doi":"10.1109/RFIC.2010.5477390","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477390","url":null,"abstract":"A co-integrated Low Noise Amplifier (LNA) with a dipole antenna is designed considering a millimeter-wave dedicated BiCMOS technology. The targeted application is a 94 GHz passive imaging for security applications. The LNA is based on a high-speed SiGe:C 130 nm HBT. The interest of the co-integration on a common silicon substrate is demonstrated through the decrease of insertion losses between the antenna and the amplifier. The capability of the BiCMOS9MW technology is illustrated to achieve this co-integration reaching a total gain of 3.0 dB (Gantenna + GLNA) for a power consumption of 11 mW, in a single-stage LNA configuration. A two-stage configuration achieves a total gain of 8.5 dB with a power consumption of 21 mW.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"290 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134302359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 65nm CMOS DCXO system for generating 38.4MHz and a real time clock from a single crystal in 0.09mm2 一种65nm CMOS DCXO系统，用于从0.09mm2的单晶产生38.4MHz和实时时钟
2010 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2010-05-23 DOI: 10.1109/RFIC.2010.5477325
D. Griffith, F. Dulger, G. Feygin, A. Mohieldin, P. Vallur
{"title":"A 65nm CMOS DCXO system for generating 38.4MHz and a real time clock from a single crystal in 0.09mm2","authors":"D. Griffith, F. Dulger, G. Feygin, A. Mohieldin, P. Vallur","doi":"10.1109/RFIC.2010.5477325","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477325","url":null,"abstract":"An integrated digitally-controlled crystal oscillator (DCXO) is presented that generates both 38.4 MHz and also a 32.768 kHz real time clock (RTC) from a single 38.4 MHz crystal. The DCXO can startup independently and transition seamlessly in and out of software control. The tuning range is 280 ppm with 2 ppb/step and guaranteed monotonicity. The phase noise is -135 dBc/Hz at 1kHz offset and -146 dBc/Hz at 10 kHz offset. The current consumption is 5 mA from a 1.4 V supply in full power mode and 234 μA in low power mode, including the LDO and all clock buffers. The DCXO is implemented in standard 65 nm digital CMOS with a die area of 0.09mm2.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134568830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
Highly linear SOI single-pole, 4-throw switch with an integrated dual-band LNA and bypass attenuators 高度线性SOI单极，4投开关，集成双频LNA和旁路衰减器
2010 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2010-05-23 DOI: 10.1109/RFIC.2010.5477363
C. Huang, L. Lam, M. Doherty, W. Vaillancourt
{"title":"Highly linear SOI single-pole, 4-throw switch with an integrated dual-band LNA and bypass attenuators","authors":"C. Huang, L. Lam, M. Doherty, W. Vaillancourt","doi":"10.1109/RFIC.2010.5477363","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477363","url":null,"abstract":"An innovative Silicon-On-Insulator (SOI) SP4T T/R switch is presented. The SP4T switch consists of 2 receive paths with an integrated dual-band LNA and bypass attenuators along with 2 high linearity matched transmit paths. Tx paths feature 0.1 dB compression to 34 dBm input power and 0.5–0.8 dB insertion loss from 1 to 6 GHz with ≫ 20 dB return loss and ≫ 25 dB isolation. Receive paths feature 16 dB gain with 2.3 dB NF for 2.4–2.5 GHz and 14 dB gain with 2.4–2.6 dB NF for 4.9–5.9 GHz. The band selectivity exceeds 40 dB. Cascading with a dual-band WLAN PA, a complex dual-band WLAN/MIMO front-end module (FEM) can be easily constructed with low assembly complexity and post PA losses resulting in dual-band transmit linearity ≫18 dBm with EVM ≪ 3% and ≪ −50 dBm/MHz harmonic emissions within a 4 × 5 mm QFN package.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124199184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A switched-capacitor mm-wave VCO in 65 nm digital CMOS 65纳米数字CMOS开关电容毫米波压控振荡器
2010 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2010-05-23 DOI: 10.1109/RFIC.2010.5477323
M. Nariman, R. Rofougaran, F. De Flaviis
{"title":"A switched-capacitor mm-wave VCO in 65 nm digital CMOS","authors":"M. Nariman, R. Rofougaran, F. De Flaviis","doi":"10.1109/RFIC.2010.5477323","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477323","url":null,"abstract":"A 34–40 GHz VCO fabricated in 65 nm digital CMOS technology is demonstrated in this paper. The VCO uses a combination of switched capacitors and varactors for tuning and has a maximum Kvco of 240 MHz/V. It exhibits a phase noise of better than −98 dBc/Hz @ 1-MHz offset across the band while consuming 12 mA from a 1.2-V supply, an FOMT of −182.1 dBc/Hz. A cascode buffer following the VCO consumes 11 mA to deliver 0 dBm LO signal to a 50Ω load.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128916366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
An integrated frequency synthesizer for 81–86GHz satellite communications in 65nm CMOS 81-86GHz卫星通信65nm CMOS集成频率合成器
2010 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2010-05-23 DOI: 10.1109/RFIC.2010.5477388
Zhiwei Xu, Q. Gu, Yi-Cheng Wu, Heng-Yu Jian, Frank Wang, Mau-Chung Frank Chang
{"title":"An integrated frequency synthesizer for 81–86GHz satellite communications in 65nm CMOS","authors":"Zhiwei Xu, Q. Gu, Yi-Cheng Wu, Heng-Yu Jian, Frank Wang, Mau-Chung Frank Chang","doi":"10.1109/RFIC.2010.5477388","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477388","url":null,"abstract":"We present an integrated frequency synthesizer in 65nm CMOS to enable the 81–86GHz satellite communication transceiver. The frequency synthesizer is inserted in a two-step zero-IF millimeter-wave transceiver with LO<inf>RF</inf> at 70–78GHz and LO<inf>IF</inf> at 1/8 of LO<inf>RF</inf> to cover the desired entire frequency bands. It also features coarse phase rotation to endow beam forming capabilities for the intended communication system. The phase noise is ≪ −83dBc/Hz at 1MHz offset as extrapolated from measured value at 1/8 of the VCO frequency (∼9.4GHz). The measured reference spur is ≪−49dBc. Total synthesizer power consumption including LO buffers and phase rotators is 65mW at 1V power supply and the compact layout has rendered small synthesizer core area of 0.16mm<sup>2</sup>.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128975551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A discrete resizing and concurrent power combining structure for linear CMOS power amplifier 一种用于线性CMOS功率放大器的离散调整尺寸和并发功率组合结构
2010 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2010-05-23 DOI: 10.1109/RFIC.2010.5477362
Jihwan Kim, Hyungwook Kim, Youngchang Yoon, K. An, Woonyun Kim, Chang-Ho Lee, K. Kornegay, J. Laskar
{"title":"A discrete resizing and concurrent power combining structure for linear CMOS power amplifier","authors":"Jihwan Kim, Hyungwook Kim, Youngchang Yoon, K. An, Woonyun Kim, Chang-Ho Lee, K. Kornegay, J. Laskar","doi":"10.1109/RFIC.2010.5477362","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477362","url":null,"abstract":"We propose a new method of power combining for a parallel-combining-transformer (PCT)-based CMOS linear power amplifier (PA). The power cell in parallel paths is divided into three sub-cells to implement device resizing for discrete power control. Concurrent power combining of sub-power-cells utilizes the maximum available transformer efficiency even at the low-power mode, boosting overall PA efficiency. When all sub-power-cells are enabled, the PA exploits output power of 30.7 dBm with PAE of 35.8%. Power back-offs of 6 dB and 12 dB are achieved by discretely turning off sub-cells, showing output power of 25 dBm and 19 dBm with PAE of 19.8% and 10.5%, respectively. With 802.11g WLAN modulated signal used for linearity test, the PA shows 21-dBm output power satisfying −25-dB EVM requirements consuming 560 mA from 3.3 V power supply.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129074408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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