2-4 and 9-12 Gb/s CMOS fully integrated ILO-based CDR

Abstract

A CDR dedicated to satellite data link is presented. The clock recovery function is made-up of an Injection Locked Oscillator combined with an analog phase alignment circuit. The circuit covers two bit-rate ranges: 2.2 to 4.3 Gb/s and 9.1 to 12.1 Gb/s. It was designed in 130 nm CMOS bulk process from STMicroelectronics. The overall power dissipation is 400 mW in the first bit-rate range and 480 mW in the second including 220 mW for I/O buffers. The eye opening at 10-9 of bit error rate is 940 mUI/440 mV at 3.1 Gb/s and 720 mUI/300 mV at 10.3 Gb/s.