基于baw的时间参考应用中频率漂移补偿的协同设计考虑

S. Razafimandimby, D. Petit, P. Bar, S. Joblot, J. Carpentier, J. Morelle, C. Arnaud1, G. Parat, P. Garcia, C. Garnier
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引用次数: 4

摘要

为了应对基于BAW时间参考的挑战,本文提出了新的BAW/集成电路(IC)协整考虑。为了演示,提出了一种SiP方法,其中固体安装谐振器(SMR)直接倒装在IC顶部。该2.5GHz振荡器在2kHz载波偏移下达到- 93dBc/Hz相位噪声,功耗为7.3mW。5bit开关电容组允许以12.5kHz精度校正工艺偏差,而变容电容允许在[- 40°C,85°C]温度范围内以- 4.2ppm/°C的频率温度系数(TCF)补偿SMR。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Co-design considerations for frequency drift compensation in BAW-based time reference application
In order to take up the challenge of BAW-based time reference, this paper presents new BAW/Integrated Circuits (IC) co-integration considerations. For the demonstration, a SiP approach is proposed where the Solidly Mounted Resonator (SMR) has been directly flip-chipped on the top of the IC. This 2.5GHz oscillator reaches a −93dBc/Hz phase noise at a 2kHz carrier offset for a 7.3mW power consumption. A 5bit switched capacitor bank permits to correct process deviations with a 12.5kHz accuracy while a varactor capacitance allows compensating a SMR with a −4.2ppm/°C Temperature Coefficient of Frequency (TCF) in a [−40°C,85°C] temperature range.
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