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2010 IEEE Radio Frequency Integrated Circuits Symposium最新文献

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A 0.045mm2 0.1–6GHz reconfigurable multi-band, multi-gain LNA for SDR 用于SDR的0.045mm2 0.1-6GHz可重构多频段多增益LNA
2010 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2010-05-23 DOI: 10.1109/RFIC.2010.5477273
A. Geis, Y. Rolain, G. Vandersteen, J. Craninckx
{"title":"A 0.045mm2 0.1–6GHz reconfigurable multi-band, multi-gain LNA for SDR","authors":"A. Geis, Y. Rolain, G. Vandersteen, J. Craninckx","doi":"10.1109/RFIC.2010.5477273","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477273","url":null,"abstract":"A low area fully reconfigurable multi-band LNA array based on active feedback amplifiers with mixed resistive and switched inductor loads is presented. The 90nm baseline digital CMOS implementation covers the entire frequency range of interest for SDR from 0.1 to 6GHz with a dynamic gain range from 0dB to 22dB. A noise figure as low as 2.7dB and an input-referred linearity IIP3 of −4dBm at 16dB gain is achieved. An IIP3 of +9dBm is reached in low gain mode to allow for high signal and interferer power at the antenna input. The LNA draws between 10 and 26mA from a 1.2V supply. The active area of the array is only 0.045mm2.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126700409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
Coherent parametric RF downconversion in CMOS CMOS中相干参数射频下变频
2010 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2010-05-23 DOI: 10.1109/RFIC.2010.5477383
Zhixing Zhao, Jean-François Bousquet, S. Magierowski
{"title":"Coherent parametric RF downconversion in CMOS","authors":"Zhixing Zhao, Jean-François Bousquet, S. Magierowski","doi":"10.1109/RFIC.2010.5477383","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477383","url":null,"abstract":"Parametric circuits constitute a longstanding RF technique that has been largely ignored by the RFIC community. Increasing interest in applying CMOS to (sub)millimeter-wave applications plus mounting scaling complexity may combine to revitalize this circuit style. This paper presents basic parametric downconverter structures, their theory of operation, and the benefits to be gained from CMOS implementation. A low-power, sub-1-V, fully integrated mixer in 130-nm CMOS is introduced. It implements two parametric modes and operates on RF signals between 22 and 24 GHz with possible conversion gains in excess of 20 dB.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121427875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A 31-dBm, high ruggedness power amplifier in 65-nm standard CMOS with high-efficiency stacked-cascode stages 一款31 dbm高坚固性功率放大器，采用65nm标准CMOS，具有高效堆叠级联
2010 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2010-05-23 DOI: 10.1109/RFIC.2010.5477401
S. Leuschner, S. Pinarello, U. Hodel, Jan-Erik Mueller, H. Klar
{"title":"A 31-dBm, high ruggedness power amplifier in 65-nm standard CMOS with high-efficiency stacked-cascode stages","authors":"S. Leuschner, S. Pinarello, U. Hodel, Jan-Erik Mueller, H. Klar","doi":"10.1109/RFIC.2010.5477401","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477401","url":null,"abstract":"A novel, high ruggedness power amplifier topology in a 65-nm CMOS technology is proposed. The proposed stacked cascode topology uses only standard devices available in a modern triple-well CMOS process to achieve breakdown voltages of more than 18V. The power amplifier stage delivers 28 dBm output power at a power-added efficiency (PAE) of 69.9% from a 3.6V supply. The saturation gain is 18 dB. A watt-level power amplifier for GSM low-band operation with 31-dBm output power and 61% PAE is presented.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"51 18","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113957724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
A D-band PLL covering the 81–82 GHz, 86–92 GHz and 162–164 GHz bands d波段锁相环，覆盖81-82 GHz、86-92 GHz和162-164 GHz频段
2010 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2010-05-23 DOI: 10.1109/RFIC.2010.5477284
S. Shahramian, A. Hart, A. Chan Carusone, P. Garcia, P. Chevalier, S. Voinigescu
{"title":"A D-band PLL covering the 81–82 GHz, 86–92 GHz and 162–164 GHz bands","authors":"S. Shahramian, A. Hart, A. Chan Carusone, P. Garcia, P. Chevalier, S. Voinigescu","doi":"10.1109/RFIC.2010.5477284","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477284","url":null,"abstract":"This paper describes the highest frequency PLL reported to date. It achieves the widest locking range and the lowest phase noise of −93.8 dBc/Hz at 90 GHz and 78.9 dBc/Hz at 163 GHz, both measured at a 100-kHz offset. The PLL was fabricated in a 0.13-µm SiGe BiCMOS process and covers the 81–82 GHz, 86–92 GHz, and 162–164 GHz bands. It integrates on a single die a fundamental-frequency 86–92 GHz Colpitts VCO, a differential push-push 160-GHz Colpitts VCO with quadrature outputs at 80 GHz, a programmable divider chain, charge-pump, and all loop filter components. The single-ended PLL output power is −3 dBm at 90 GHz and −25 dBm at 164 GHz and consumes 1.25 W from 1.8-V, 2.5-V and 3.3-V supplies. The chip occupies 1.1mm × 1.7mm including pads.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125984375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
A low power low cost fully integrated UHF RFID reader with 17.6dBm output P1dB in 0.18 µm CMOS process 低功耗低成本完全集成的UHF RFID阅读器，输出P1dB为17.6dBm，采用0.18µm CMOS工艺
2010 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2010-05-23 DOI: 10.1109/RFIC.2010.5477299
Jingchao Wang, Chun Zhang, Zhihua Wang
{"title":"A low power low cost fully integrated UHF RFID reader with 17.6dBm output P1dB in 0.18 µm CMOS process","authors":"Jingchao Wang, Chun Zhang, Zhihua Wang","doi":"10.1109/RFIC.2010.5477299","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477299","url":null,"abstract":"A low power low cost fully integrated single-chip UHF radio frequency identification (RFID) reader for short distance handheld applications is presented in this paper. The IC integrates all building blocks—including an RF transceiver, a PLL frequency synthesizer, a digital baseband and a MCU—in a 0.18 µm CMOS process. A high-linearity RX front-end and a low-phase-noise synthesizer are designed to handle the large self-interferer. A class-E power amplifier with high power efficiency is also integrated to fulfill the function of a UHF passive RFID reader. The measured output P1dB power of the transmitter is 17.6dBm and the measured receiver sensitivity is −60dBm. The digital baseband including MCU core consumes 3.9mW with a clock of 10MHz and the analog part including power amplifier consumes 281.5mW. The chip has a die area of 5.1mm*3.8mm including pads.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129981166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 17 GHz transformer-neutralized current re-use LNA and its application to a low-power RF front-end 一种17ghz变压器中和电流复用LNA及其在低功率射频前端的应用
2010 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2010-05-23 DOI: 10.1109/RFIC.2010.5477286
S. Kundu, J. Paramesh
{"title":"A 17 GHz transformer-neutralized current re-use LNA and its application to a low-power RF front-end","authors":"S. Kundu, J. Paramesh","doi":"10.1109/RFIC.2010.5477286","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477286","url":null,"abstract":"A 17 GHz current re-use low noise amplifier (LNA) is designed in 0.13 µm CMOS for low power applications such as wireless sensor networks. The LNA also employs transformer based feedback to neutralize the gate-drain capacitance of a MOSFET. The LNA achieves 15.4 dB gain into a 50 Ω load along with 1.9 GHz bandwidth. It features 4.5dB NF and −12 dBm IIP3 while consuming 7.8 mW of power. A 17 GHz receiver frontend using a similar two-stage LNA and a mixer is also demonstrated which achieves 25 dB of voltage conversion gain at 70 MHz IF, 7 dB NF, −18 dBm IIP3 and consumes 8 mW from a 1.2 V supply.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134294516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
The impact of MOSFET layout dependent stress on high frequency characteristics and flicker noise 基于应力的MOSFET布局对高频特性和闪烁噪声的影响
2010 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2010-05-23 DOI: 10.1109/RFIC.2010.5477296
K. Yeh, Chih-You Ku, Jyh-Chyurn Guo
{"title":"The impact of MOSFET layout dependent stress on high frequency characteristics and flicker noise","authors":"K. Yeh, Chih-You Ku, Jyh-Chyurn Guo","doi":"10.1109/RFIC.2010.5477296","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477296","url":null,"abstract":"Layout dependent stress in 90 nm MOSFET and its impact on high frequency performance and flicker noise has been investigated. Donut MOSFETs were created to eliminate the transverse stress from shallow trench isolation (STI). Both NMOS and PMOS can benefit from the donut layout in terms of higher effective mobility μeff and cutoff frequency fT, as well as lower flicker noise. The measured flicker noise follows number fluctuation model for NMOS and mobility fluctuation model for PMOS, respectively. The reduction of flicker noise suggests the reduction of STI generated traps and the suppression of mobility fluctuation due to eliminated transverse stress using donut structure.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133038956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A broadband differential cascode power amplifier in 45 nm CMOS for high-speed 60 GHz system-on-chip 用于高速60 GHz片上系统的45 nm CMOS宽带差分级联码功率放大器
2010 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2010-05-23 DOI: 10.1109/RFIC.2010.5477384
M. Abbasi, T. Kjellberg, A. de Graauw, E. van der Heijden, R. Roovers, H. Zirath
{"title":"A broadband differential cascode power amplifier in 45 nm CMOS for high-speed 60 GHz system-on-chip","authors":"M. Abbasi, T. Kjellberg, A. de Graauw, E. van der Heijden, R. Roovers, H. Zirath","doi":"10.1109/RFIC.2010.5477384","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477384","url":null,"abstract":"A compact two-stage differential cascode power amplifier is designed and fabricated in 45 nm standard LP CMOS. The cascode configuration, with the common gate device placed in a separate P-well, provides reliable operating condition for the devices. The amplifier shows 20 dB small-signal gain centered at 60 GHz with a flat frequency response and 1-dB bandwidth of 10 GHz. The broadband large-signal operation is also ensured by providing constant load resistance to both stages over the entire band and coupling them with a dual resonance matching network. The chip delivers 11.2 dBm output power at 1-dB compression and up to 14.5 dBm power in saturation. The power amplifier operates with 2 V supply and draws 90 mA total current which results in 14.4% maximum PAE. The output third order intercept point is measured to be 18 dBm for two-tone measurement at 60 GHz with 0.5 GHz, 1 GHz and 2 GHz frequency separations.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133121177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
Integration of multi-standard front end modules SOCs on high resistivity SOI RF CMOS technology 在高电阻率SOI RF CMOS技术上集成多标准前端模块soc
2010 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2010-05-23 DOI: 10.1109/RFIC.2010.5477370
F. Gianesello, S. Boret, B. Martineau, C. Durand, R. Pilard, D. Gloria, B. Rauber, C. Raynaud
{"title":"Integration of multi-standard front end modules SOCs on high resistivity SOI RF CMOS technology","authors":"F. Gianesello, S. Boret, B. Martineau, C. Durand, R. Pilard, D. Gloria, B. Rauber, C. Raynaud","doi":"10.1109/RFIC.2010.5477370","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477370","url":null,"abstract":"RF front end modules (FEMs) are currently realized using a variety of technologies. However, since integration drives wireless business in order to achieve the appropriate cost and form factor, we see significant research concerning FEM integration on silicon [1]. In this quest, SOI technology has already addressed two key blocks, the antenna switch and the power amplifier. In this paper, we will focus our investigation on high performance passive functions in order to demonstrate the capability of SOI CMOS technology to integrate the whole FEM. To do so, balun, harmonic filter, diplexer and directional coupler have been achieved in a 130 nm SOI CMOS technology. Measured performances are clearly competitive with most commercially available Integrated Passive Device (IPD) solutions, which paves the way of FEM silicon SOCs.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133838049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 0.13-µm CMOS local oscillator for 60-GHz applications based on push-push characteristic of capacitive degeneration 基于电容退化推推特性的60 ghz 0.13µm CMOS本振
2010 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2010-05-23 DOI: 10.1109/RFIC.2010.5477283
T. Copani, Hyung-Seuk Kim, B. Bakkaloglu, S. Kiaei
{"title":"A 0.13-µm CMOS local oscillator for 60-GHz applications based on push-push characteristic of capacitive degeneration","authors":"T. Copani, Hyung-Seuk Kim, B. Bakkaloglu, S. Kiaei","doi":"10.1109/RFIC.2010.5477283","DOIUrl":"https://doi.org/10.1109/RFIC.2010.5477283","url":null,"abstract":"A 60-GHz 10mW CMOS VCO is implemented together with a high-speed prescaler in a 130nm CMOS process. Compared to other push-push topologies, capacitive degeneration technique does not impact the resonator and switching transistors are re-used as buffers minimizing noise due to following amplifiers. The measured phase noise at 1MHz offset is −89dBc/Hz and FoM is −174dBc/Hz.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114390969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
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