A D-band PLL covering the 81–82 GHz, 86–92 GHz and 162–164 GHz bands

This paper describes the highest frequency PLL reported to date. It achieves the widest locking range and the lowest phase noise of −93.8 dBc/Hz at 90 GHz and 78.9 dBc/Hz at 163 GHz, both measured at a 100-kHz offset. The PLL was fabricated in a 0.13-µm SiGe BiCMOS process and covers the 81–82 GHz, 86–92 GHz, and 162–164 GHz bands. It integrates on a single die a fundamental-frequency 86–92 GHz Colpitts VCO, a differential push-push 160-GHz Colpitts VCO with quadrature outputs at 80 GHz, a programmable divider chain, charge-pump, and all loop filter components. The single-ended PLL output power is −3 dBm at 90 GHz and −25 dBm at 164 GHz and consumes 1.25 W from 1.8-V, 2.5-V and 3.3-V supplies. The chip occupies 1.1mm × 1.7mm including pads.