用于高速60 GHz片上系统的45 nm CMOS宽带差分级联码功率放大器

M. Abbasi, T. Kjellberg, A. de Graauw, E. van der Heijden, R. Roovers, H. Zirath
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引用次数: 32

摘要

设计并制作了一种紧凑的两级差分级联码功率放大器。级联编码配置,将公共栅极装置放置在单独的p井中,为设备提供可靠的工作条件。该放大器显示以60ghz为中心的20db小信号增益,频率响应平坦,1db带宽为10ghz。通过在整个频带上为两个级提供恒定的负载阻力,并通过双共振匹配网络将它们耦合起来,也确保了宽带大信号操作。该芯片在1db压缩时输出功率为11.2 dBm,饱和时输出功率高达14.5 dBm。功率放大器在2 V电源下工作,总电流为90 mA,最大PAE为14.4%。输出三阶截距点测量为18 dBm,用于60 GHz双音测量,频率间隔为0.5 GHz, 1 GHz和2 GHz。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A broadband differential cascode power amplifier in 45 nm CMOS for high-speed 60 GHz system-on-chip
A compact two-stage differential cascode power amplifier is designed and fabricated in 45 nm standard LP CMOS. The cascode configuration, with the common gate device placed in a separate P-well, provides reliable operating condition for the devices. The amplifier shows 20 dB small-signal gain centered at 60 GHz with a flat frequency response and 1-dB bandwidth of 10 GHz. The broadband large-signal operation is also ensured by providing constant load resistance to both stages over the entire band and coupling them with a dual resonance matching network. The chip delivers 11.2 dBm output power at 1-dB compression and up to 14.5 dBm power in saturation. The power amplifier operates with 2 V supply and draws 90 mA total current which results in 14.4% maximum PAE. The output third order intercept point is measured to be 18 dBm for two-tone measurement at 60 GHz with 0.5 GHz, 1 GHz and 2 GHz frequency separations.
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