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Novel AlInN/GaN integrated circuits operating up to 500 °C 新颖的AlInN/GaN集成电路工作温度高达500°C
2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-11-06 DOI: 10.1109/ESSDERC.2014.6948778
R. Gaska, M. Gaevski, J. Deng, R. Jain, G. Simin, M. Shur
{"title":"Novel AlInN/GaN integrated circuits operating up to 500 °C","authors":"R. Gaska, M. Gaevski, J. Deng, R. Jain, G. Simin, M. Shur","doi":"10.1109/ESSDERC.2014.6948778","DOIUrl":"https://doi.org/10.1109/ESSDERC.2014.6948778","url":null,"abstract":"High-temperature technology platform has been developed based on AlInN/GaN heterostructures. High electron concentration in 2DEG channel of AlInN/GaN devices is remarkably stable over a broad temperature range, enabling device operation above 500 °C. The developed IC technology is based on three key elements: (1) exceptional quality AlInN/GaN heterostructure with very high carrier concentration and mobility that enables IC fast operation in a broad temperature range; (2) heterostructure field effect transistor approach that provides fully planar IC structure which is easy to scale and to combine with the other high temperature electronic components; (3) fabrication advancements including novel metallization scheme and high-k passivation/gate dielectrics, specifically developed for high temperature operation. The feasibility of the technology was demonstrated by fabrication and testing inverter and differential amplifier ICs using AlInN/GaN heterostructures. At temperature exceeding 500°C, the developed ICs show stable performance with unit-gain bandwidth above 1 MHz and internal response time 45 ns*.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116069869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
Operation of Lorentz-force MEMS magnetometers with on-off current switching 具有开关电流开关的洛伦兹力MEMS磁强计的操作
2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-11-06 DOI: 10.1109/ESSDERC.2014.6948758
G. Langfelder, C. Buffa, P. Minotti, A. Longoni, A. Tocchio, S. Zerbini
{"title":"Operation of Lorentz-force MEMS magnetometers with on-off current switching","authors":"G. Langfelder, C. Buffa, P. Minotti, A. Longoni, A. Tocchio, S. Zerbini","doi":"10.1109/ESSDERC.2014.6948758","DOIUrl":"https://doi.org/10.1109/ESSDERC.2014.6948758","url":null,"abstract":"Combined off-resonance operation and on-off switching of the driving current is applied to a micro-electromechanical systems (MEMS) magnetometer. This novel driving technique allows improving the signal to noise ratio (SNR), and thus the minimum measurable magnetic field, with no added cost in terms of driving current. The technique is applied to a magnetometer built in a surface micromachining process. Measurements show a 5.4 times better resolution than for operation at resonance in continuous mode.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126603244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Joint impact of random variations and RTN on dynamic writeability in 28nm bulk and FDSOI SRAM 随机变化和RTN对28nm块体和FDSOI SRAM动态可写性的共同影响
2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-11-06 DOI: 10.1109/ESSDERC.2014.6948767
B. Zimmer, O. Thomas, S. Toh, Taylor Vincent, K. Asanović, B. Nikolić
{"title":"Joint impact of random variations and RTN on dynamic writeability in 28nm bulk and FDSOI SRAM","authors":"B. Zimmer, O. Thomas, S. Toh, Taylor Vincent, K. Asanović, B. Nikolić","doi":"10.1109/ESSDERC.2014.6948767","DOIUrl":"https://doi.org/10.1109/ESSDERC.2014.6948767","url":null,"abstract":"Improving SRAM minimum operating voltage (Vmin) in scaled process nodes requires characterization of different failure mechanisms. Persistent errors caused by random variations and intermittent errors caused by random telegraph noise (RTN) both contribute to bitcell failure. Random Vth shift was measured for 32,000 in-situ SRAM cells in both 28 nm bulk and FDSOI processes due to both random variations and RTN, and dynamic writeability was measured by two different write modes that accentuate different RTN behaviour. Measured distribution parameters of both random variation and RTN were used to calibrate an accelerated Monte Carlo simulation that predicts a Vmin difference due to RTN. Measurements show that while FDSOI technology reduces random variation by approximately 27% compared to bulk, similar RTN amplitudes slightly increase bitcell susceptibility to failures caused by RTN.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126951089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Analysis of failure mechanisms in erased state of sub 20-nm NAND Flash memory 亚20nm NAND闪存擦除失效机理分析
2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-11-06 DOI: 10.1109/ESSDERC.2014.6948757
Kyunghwan Lee, Duckseoung Kang, Hyungcheol Shin, S. Kwon, Shinhyung Kim, Yuchul Hwang
{"title":"Analysis of failure mechanisms in erased state of sub 20-nm NAND Flash memory","authors":"Kyunghwan Lee, Duckseoung Kang, Hyungcheol Shin, S. Kwon, Shinhyung Kim, Yuchul Hwang","doi":"10.1109/ESSDERC.2014.6948757","DOIUrl":"https://doi.org/10.1109/ESSDERC.2014.6948757","url":null,"abstract":"In this paper, we analyzed the characteristics of dominant failure mechanisms in the erased (ERS) state of sub 20-nm NAND Flash memory with an accurate compact model. As a result, it was observed that various charge loss and charge gain mechanisms are mixed together. While the detrapping and the interface trap recovery (Nit) mechanism contribute to the charge loss, the trap-assisted tunneling (TAT) is the charge gain mechanism in the ERS state due to the negative electric field across tunneling oxide layer. At the less cycled cells, the charge gain is dominant due to the TAT mechanism. However, as increasing the cycling times, the detrapping component becomes larger by trapped carriers and the TAT component gets reduced as the detrapped electrons raise the energy level of floating gate (FG) and energy barrier of tunneling oxide layer. Therefore, the charge loss becomes dominant at increased cycling times.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128025483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Internal photoemission technique for high-k oxide/semiconductor band offset determination: The influence of semiconductor bulk properties 高k氧化物/半导体带偏置测定的内部光电发射技术:半导体体特性的影响
2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-11-06 DOI: 10.1109/ESSDERC.2014.6948837
O. Engström, H. Przewlocki, I. Mitrovic, S. Hall
{"title":"Internal photoemission technique for high-k oxide/semiconductor band offset determination: The influence of semiconductor bulk properties","authors":"O. Engström, H. Przewlocki, I. Mitrovic, S. Hall","doi":"10.1109/ESSDERC.2014.6948837","DOIUrl":"https://doi.org/10.1109/ESSDERC.2014.6948837","url":null,"abstract":"A method for extracting energy band alignment of metal/high-k oxide/semiconductor structures from internal photoemission experiments is discussed by modeling the excitation and relaxation processes taking place in the semiconductor at photon irradiation. Classical literature data on photoemission of electrons from silicon and germanium surfaces into vacuum is compared with more recently published data on HfO2/Si and HfO2/Ge structures to identify characteristic features of photoelectric yield. We find that a dominating structure of such spectra, which often has been assumed to originate from the oxide barrier, derives from the energy dependence of absorption coefficient and mean free paths of excited electrons. Our results indicate that most IPE data on high-k oxide/silicon and germanium structures need re-interpretation.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"321 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122733848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
CMOS VT characterization by capacitance measurements in FDSOI PIN gated diodes 用电容测量FDSOI引脚门控二极管的CMOS VT特性
2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-11-06 DOI: 10.1109/ESSDERC.2014.6948846
C. Navarro, M. Bawedin, F. Andrieu, J. Cluzel, X. Garros, S. Cristoloveanu
{"title":"CMOS VT characterization by capacitance measurements in FDSOI PIN gated diodes","authors":"C. Navarro, M. Bawedin, F. Andrieu, J. Cluzel, X. Garros, S. Cristoloveanu","doi":"10.1109/ESSDERC.2014.6948846","DOIUrl":"https://doi.org/10.1109/ESSDERC.2014.6948846","url":null,"abstract":"We present a powerful technique for the characterization of FDSOI devices. For example, in CMOS designs, the evaluation of threshold voltage for N and also P-MOSFETs is compulsory and is performed in separate devices. We propose to extract the threshold voltage for both types of transistors simultaneously by using capacitance measurements in thin fully depleted SOI PIN gated diodes. The N+ and P+ terminals guarantee the availability of both types of carrier and equilibrium conditions during all operation modes: from strong accumulation to strong inversion. Experiments together with numerical TCAD simulations are performed and discussed. It is shown that, from a single capacitance curve, it is possible to extract also the threshold voltage at the bottom interface.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129501631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
The Factory Integration Roadmap in Semiconductor manufacturing 半导体制造中的工厂集成路线图
2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-11-06 DOI: 10.1109/ESSDERC.2014.6948781
J. Moyne, M. Schellenberger, L. Pfitzner
{"title":"The Factory Integration Roadmap in Semiconductor manufacturing","authors":"J. Moyne, M. Schellenberger, L. Pfitzner","doi":"10.1109/ESSDERC.2014.6948781","DOIUrl":"https://doi.org/10.1109/ESSDERC.2014.6948781","url":null,"abstract":"The International Technology Roadmap for Semiconductors (ITRS) is probably the single most important document governing the direction of the semiconductor manufacturing industry. The Factory Integration (FI) chapter seeks to define a roadmap for semiconductor factories and enterprise systems. This roadmap has gone through a significant revision over the past 2 years with a focus on commonality, integration, and data driven. New sub-chapters have been created for prediction, big data, and control systems architectures. Challenges and potential solutions have been identified for each of these sub-chapters, some of which are common across industries, and others of which are unique to the semiconductor manufacturing industry.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133215427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Improvement of epitaxial channel quality on heavily arsenic- and boron-doped Si surfaces and impact on tunnel FET performance 高掺砷硼硅表面外延沟道质量的改善及其对隧道场效应管性能的影响
2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-11-06 DOI: 10.1109/ESSDERC.2014.6948790
Y. Morita, T. Mori, S. Migita, W. Mizubayashi, K. Fukuda, T. Matsukawa, K. Endo, S. O'Uchi, Yongxun Liu, M. Masahara, H. Ota
{"title":"Improvement of epitaxial channel quality on heavily arsenic- and boron-doped Si surfaces and impact on tunnel FET performance","authors":"Y. Morita, T. Mori, S. Migita, W. Mizubayashi, K. Fukuda, T. Matsukawa, K. Endo, S. O'Uchi, Yongxun Liu, M. Masahara, H. Ota","doi":"10.1109/ESSDERC.2014.6948790","DOIUrl":"https://doi.org/10.1109/ESSDERC.2014.6948790","url":null,"abstract":"We evaluate the impact of tunnel junction quality on the performance of tunnel field-effect transistors (TFETs). Performing a sequential surface cleaning procedure prior to epitaxial channel growth for heavily arsenic- and boron-doped Si surfaces improves the interface quality both for p- and n-TFETs. Simultaneously, the subthreshold swing (SS) values of the TFETs improve step-by-step with interface quality.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129731539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
MOSFET degradation under DC and RF Fowler-Nordheim stress 直流和射频福勒-诺德海姆应力下MOSFET的退化
2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-11-06 DOI: 10.1109/ESSDERC.2014.6948802
A. Cattaneo, S. Pinarello, J. Mueller, R. Weigel
{"title":"MOSFET degradation under DC and RF Fowler-Nordheim stress","authors":"A. Cattaneo, S. Pinarello, J. Mueller, R. Weigel","doi":"10.1109/ESSDERC.2014.6948802","DOIUrl":"https://doi.org/10.1109/ESSDERC.2014.6948802","url":null,"abstract":"Fowler-Nordheim (F-N) stress is reported to be one of the most severe wear-out mechanisms for high-frequency MOSFET applications like PAs and RF switches. Previous studies of this degradation process were limited to the DC-static case only and standard empirical models were proposed. In this work a novel general physical model is developed, which correctly describes the ageing of electrical parameters under DC stress. This is made possible by taking into account the hole injection into the gate oxide. Finally this study extends the understanding of F-N degradation to RF regime. In this case a quasi-static sum of the degradation rate is adopted to accurately model and predict the performance worsening; the wear-out shows no frequency dependency in the range up to 4Ghz.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133420923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Qualitative assessment of epitaxial graphene FETs on SiC substrates via pulsed measurements and temperature variation 通过脉冲测量和温度变化对SiC衬底外延石墨烯场效应管进行定性评价
2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-11-06 DOI: 10.1109/ESSDERC.2014.6948821
C. Mukherjee, S. Frégonèse, T. Zimmer, C. Maneux, H. Happy, David Mele
{"title":"Qualitative assessment of epitaxial graphene FETs on SiC substrates via pulsed measurements and temperature variation","authors":"C. Mukherjee, S. Frégonèse, T. Zimmer, C. Maneux, H. Happy, David Mele","doi":"10.1109/ESSDERC.2014.6948821","DOIUrl":"https://doi.org/10.1109/ESSDERC.2014.6948821","url":null,"abstract":"In this paper, we report a qualitative study on the performances of Graphene on SiC FETs from pulsed measurements as a function of temperature variation, reflecting on the process quality of the graphene FETs. Currents and transconductances in both pulsed and DC measurements as a function of temperature in the 25°C to 75°C range do not show any significant variation which indicates a trap-free interface and good graphene quality as well as thermal stability. In order to get a complete picture, scattering parameters from pulsed measurements are also given and the extracted gate capacitances and resistances, cut-off frequencies and fMAX are shown at different temperatures. As a whole, our study illustrates the stability, robustness and applicability of this graphene technology for future high performance electronics.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127199596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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