2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225)最新文献

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Worldwide packaging trends for portable products 便携式产品的全球包装趋势
2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225) Pub Date : 1998-04-15 DOI: 10.1109/IEMTIM.1998.704623
T. Goodman, E.J. Vardaman, K. Otsuka
{"title":"Worldwide packaging trends for portable products","authors":"T. Goodman, E.J. Vardaman, K. Otsuka","doi":"10.1109/IEMTIM.1998.704623","DOIUrl":"https://doi.org/10.1109/IEMTIM.1998.704623","url":null,"abstract":"The main drivers for packaging in highly functional, miniaturized portable products are small form factor and cost. Established technologies such as quad flat packs (QFP) and small outline packages (SOP) have been available to designers for years. Recently, a multitude of packaging solutions have been developed to meet the needs of future portable products. Many companies are tuning to small, high density mounting in the form of ball grid arrays (BGA), chip-size packages (CSP), and flip chip. The choice of technology is based on a portable product's requirements for performance (including size) and cost (including manufacturability). Examination of a number of current products shows an array of different technology mixes. Despite the proliferation of new high density mounting worldwide, many companies are satisfying current needs with peripherally leaded QFPs and SOPs. The high density mounting in some of these products is limited to small multichip packages (MCP) and daughter boards.","PeriodicalId":260028,"journal":{"name":"2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132824874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
High performance photo-sensitive insulating materials for high density multi-layer wiring boards 用于高密度多层线路板的高性能光敏绝缘材料
2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225) Pub Date : 1998-04-15 DOI: 10.1109/IEMTIM.1998.704522
M. Morishima, H. Akahoshi, M. Kawamoto, T. Suwa, M. Miyazaki, H. Fukai
{"title":"High performance photo-sensitive insulating materials for high density multi-layer wiring boards","authors":"M. Morishima, H. Akahoshi, M. Kawamoto, T. Suwa, M. Miyazaki, H. Fukai","doi":"10.1109/IEMTIM.1998.704522","DOIUrl":"https://doi.org/10.1109/IEMTIM.1998.704522","url":null,"abstract":"The photo-via build-up process is a most significant candidate for fabrication of high density multi-layer wiring boards for high density packaging using CSP and flip-chip direct attach. We have developed a new type of photo-sensitive dielectric. The dielectric delivers high resolution in fabrication of photoformed microvia holes with an aspect ratio of 1.0. The photo-sensitive dielectric showed excellent electrical and mechanical properties for surface mounted wiring boards. It also shows outstanding mechanical properties, especially in the high temperature region. Excellent insulating properties and adhesion were proven, even after pressure cooker test (PCT) conditions. These features offer a great advantage in achieving higher interconnect reliability in direct-chip attachment on low cost multichip modules using sequential build-up substrates.","PeriodicalId":260028,"journal":{"name":"2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132947597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Hybrid power modules using a metal matrix composite baseplate: An evaluation 采用金属基复合材料基板的混合动力模块:评价
2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225) Pub Date : 1998-04-15 DOI: 10.1109/IEMTIM.1998.704558
S. Azzopardi, J.-M. Thebaud, E. Woirgard, C. Zardini
{"title":"Hybrid power modules using a metal matrix composite baseplate: An evaluation","authors":"S. Azzopardi, J.-M. Thebaud, E. Woirgard, C. Zardini","doi":"10.1109/IEMTIM.1998.704558","DOIUrl":"https://doi.org/10.1109/IEMTIM.1998.704558","url":null,"abstract":"This paper presents an evaluation of the reliability of hybrid power modules using a metal matrix composite baseplate. In this study, we investigate the possible damage in the assemblies by measuring their thermal resistance. Several 2\"/spl times/1\" power module samples including four bipolar transistors (BUX48) have been realized with the use of a vacuum bake soldering machine allowing reduction of voids in the solder joints. The test vehicles have been submitted to liquid-liquid thermal shocks (+125/spl deg/C/-55/spl deg/C). Every 250 thermal shocks, two samples were extracted in order to measure the thermal resistance. Results show that even after 2700 shocks, only a very small increase in the thermal resistance of the assemblies is observed. In comparison, modules with a copper baseplate show a strong increase in thermal resistance and fail much earlier. As a consequence, in applications where thermal cycling is involved, hybrid power modules with metal matrix composite baseplates will offer much better reliability. SEM observations conducted on cross-sectioned samples and acoustic analysis do not show the typical cracks generally observed in solder joints between the direct bonded copper substrate and the copper baseplate of aged modules.","PeriodicalId":260028,"journal":{"name":"2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114298724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Vertical microvia connections achieved using a unique conductive composite material 垂直微孔连接采用独特的导电复合材料
2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225) Pub Date : 1998-04-15 DOI: 10.1109/IEMTIM.1998.704665
G. Matijasevic, P. Gandhi, C. Gallagher
{"title":"Vertical microvia connections achieved using a unique conductive composite material","authors":"G. Matijasevic, P. Gandhi, C. Gallagher","doi":"10.1109/IEMTIM.1998.704665","DOIUrl":"https://doi.org/10.1109/IEMTIM.1998.704665","url":null,"abstract":"A novel base technology applicable to all major packaging and redistribution elements in an electronic module is presented. A unique polymer/metal composite conductor family based on transient liquid phase sintering (TLPS) can be used for chip package and PWB substrate applications, in interlayer connections, and for SMT assembly. High density multilayer circuits with landless blind and buried vias are fabricated by conductor paste filling of photoimaged dielectrics and thermal processing. Via layers are similarly prepared directly on the inherently planarized circuit layer. Circuit traces as fine as 50 /spl mu/m lines/spaces and vias as small as 75 /spl mu/m have been produced. Building up layers sequentially in this way allows additive fabrication on various materials, including metal substrates. These organic-metallic Ormet/sup (R)/ composites have also been used in interlayer connections between two-sided circuits to form vertical interconnects between circuit pads. This parallel build-up approach uses a standard lamination process to achieve vertical connections. Vias less than 100 /spl mu/m have been used to connect the pads. Fine line two-sided circuits can also be attached as a patch to low density boards to provide localized high density areas. Variations of the composite conductor can also replace solder for surface mount and COB assembly. These reliable, high thermal/electrical conductivity materials are compatible with standard metal finishes of conventional technologies and can be used piecemeal as desired, but the largest reliability and cost benefit is realized when all of the elements are used together.","PeriodicalId":260028,"journal":{"name":"2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127218914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A new concept for microwave MCMs 微波mcm的新概念
2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225) Pub Date : 1998-04-15 DOI: 10.1109/IEMTIM.1998.704630
L. Bergstedt, K. Boustedt
{"title":"A new concept for microwave MCMs","authors":"L. Bergstedt, K. Boustedt","doi":"10.1109/IEMTIM.1998.704630","DOIUrl":"https://doi.org/10.1109/IEMTIM.1998.704630","url":null,"abstract":"The drive in the industry towards smaller, lighter, more efficient products encompasses all types of products, including microwave communication. At Ericsson Microwave Systems, customer demand for a product which integrates the microwave control unit with the antenna in the mast has been noted. This means that the indoor control units become redundant and there is less hardware. This packaging concept is based on the fact that the electronics are placed behind the flat antenna unit for efficient use of the available area. The technical concept is a multilayer PTFE thermoplastic motherboard design and split-function MCMs with possibilities for buried capacitors etc. The chip environment is split between the MCM and the motherboard. The motherboard has shielded conductors and a common ground plane with the MCM. The chips are placed level with the substrate to which they are connected with bond wires, and therefore the wires can be made shorter than if the chips were placed on the board as in ordinary chip and wire cases. The reduced wire length is most significant in order to achieve good electrical performance. To meet market demand, we have designed an electronics packaging system for multi-frequency purposes, for products ranging from 5-40 GHz. Current antenna integrated electronics are mostly military applications designed in exclusive materials for advanced production methods. On entering a market for commercial applications, new methods must be implemented to reach cost-effective targets. This paper presents some possible methods for reaching this goal.","PeriodicalId":260028,"journal":{"name":"2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121325900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
'Hibridas' photoimageable thick film process and materials for microwave and sensor component applications 用于微波和传感器元件应用的“Hibridas”光成像厚膜工艺和材料
2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225) Pub Date : 1998-04-15 DOI: 10.1109/IEMTIM.1998.704546
S. Muckett, Jurate Minalgene
{"title":"'Hibridas' photoimageable thick film process and materials for microwave and sensor component applications","authors":"S. Muckett, Jurate Minalgene","doi":"10.1109/IEMTIM.1998.704546","DOIUrl":"https://doi.org/10.1109/IEMTIM.1998.704546","url":null,"abstract":"The 'Hibridas' photoimageable thick film process was originally developed by the Microelectronics department of the Research Institute for Radiomeasurement Engineering (now Hibridas Enterprise Ltd.) during the early 1980s. Using this process, it is possible to achieve thick film conductor line and space resolutions of 20 /spl mu/m/30 /spl mu/m at a fired film thickness of 10 /spl mu/m on a standard alumina substrate. The Hibridas process equipment is described, and the performance of microwave devices and sensor components produced with Hibridas thick film materials are reported. The results show that photoimageable thick film technology may be of great interest to designers and producers of thick film circuits and components for applications where extremely fine line geometries and resolutions are required.","PeriodicalId":260028,"journal":{"name":"2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126688326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Capacitors embedded in the low temperature cofired ceramics 嵌入在低温共烧陶瓷中的电容器
2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225) Pub Date : 1998-04-15 DOI: 10.1109/IEMTIM.1998.704519
L.S. Chen, S. Fu, K.-D. Huang
{"title":"Capacitors embedded in the low temperature cofired ceramics","authors":"L.S. Chen, S. Fu, K.-D. Huang","doi":"10.1109/IEMTIM.1998.704519","DOIUrl":"https://doi.org/10.1109/IEMTIM.1998.704519","url":null,"abstract":"With the addition of LiF, nonstoichiometric barium titanate can be densified well after sintering at temperatures of less than 1000/spl deg/C, which is compatible with LTCC substrates. From the X-ray diffraction pattern, barium titanate is the main existing crystalline structure. On the observation of the microstructure, no delamination between substrate and capacitor layer is observed after cofiring. Both the capacitance and dissipation factor are stable over the -30/spl deg/C to 150/spl deg/C range.","PeriodicalId":260028,"journal":{"name":"2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114899769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Micro/chip scale packages and the semiconductor industry road map 微/芯片规模封装和半导体产业路线图
2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225) Pub Date : 1998-04-15 DOI: 10.1109/IEMTIM.1998.704664
C. E. Bauer
{"title":"Micro/chip scale packages and the semiconductor industry road map","authors":"C. E. Bauer","doi":"10.1109/IEMTIM.1998.704664","DOIUrl":"https://doi.org/10.1109/IEMTIM.1998.704664","url":null,"abstract":"Micro/chip scale packages are the hot topic in the IC packaging industry at present, but important questions regarding the fit between advances in IC technology and packaging technology remain unanswered. By exploring the recently published Semiconductor Industry Association (SIA) semiconductor technology road map, some of the answers are forthcoming, particularly with regard to the role of miniaturization of IC packages. In addition to concerns about miniaturization, several materials and process challenges are identified, along with strategies for solution development. Once the challenges of IC packaging are overcome, the next step will require substantial care to avoid raising major entry barriers to the use of these packages. The established design and assembly infrastructure throughout the world cannot adapt overnight to the whims of the IC packager. Thus the challenges of printed wiring board design and fabrication, component handling and placement, attachment methods, etc., must also be addressed. These multidisciplinary considerations provide for two alternative paths to meet the needs of the electronics industry's varied packaging, interconnection and assembly objectives. One path, technological convergence, melds the materials and process requirements of packaging and interconnection. The other path, technology integration, transfers the packaging requirements further down the value delivery chain.","PeriodicalId":260028,"journal":{"name":"2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225)","volume":"162 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122472904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Modeling and characterization studies of parasitic elements in lead-on-chip thin-small-outline packaging 片上铅薄型小轮廓封装中寄生元件的建模与表征研究
2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225) Pub Date : 1998-04-15 DOI: 10.1109/IEMTIM.1998.704661
Pak-Hong Yee, Siu-Waf Low, Y. Swee
{"title":"Modeling and characterization studies of parasitic elements in lead-on-chip thin-small-outline packaging","authors":"Pak-Hong Yee, Siu-Waf Low, Y. Swee","doi":"10.1109/IEMTIM.1998.704661","DOIUrl":"https://doi.org/10.1109/IEMTIM.1998.704661","url":null,"abstract":"Parameters affecting the parastic elements of a lead-on-chip (LOC) thin small outline package (TSOP) were studied by modeling with a TI internal RLC extractor and measurement technique using a vector network analyzer (VNA). Variation in the resistance (R), inductance (L) and capacitance (C) of a TSOP with respect to changes in the lead dimensions were assessed by modeling with a line-and-space pattern based on the TSOP geometry. The effect on RLC due to changes in the lead-to-ground separation, electrical properties of the materials and frequency were assessed by modeling based on a 54-pin TSOP applied to 64 Mb/spl times/16 SDRAM. Measurement was made to confirm the frequency dependence of RLC for Alloy42 (A42), copper (Cu) and palladium plated copper (Pd-Cu) as leadframe material. Some fundamentals for packaging design are summarized. For instance, L can be reduced by increasing lead width and decreasing lead-to-ground separation simultaneously. In frequency studies, it is found that the A42 leadframe has a higher frequency dependence on R and L, and is thus electrically inferior to Cu and Pd-Cu leadframes.","PeriodicalId":260028,"journal":{"name":"2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125015081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Coupling of spot-size converted laser diode to polymeric waveguide with 45-degree micro reflection mirror for optical surface mount technology 光斑转换激光二极管与45度微反射镜聚合物波导耦合的光学表面贴装技术
2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225) Pub Date : 1998-04-15 DOI: 10.1109/IEMTIM.1998.704535
T. Satoh, A. Ichimura, O. Mikami, S. Tomaru, M. Hikita, T. Uchida
{"title":"Coupling of spot-size converted laser diode to polymeric waveguide with 45-degree micro reflection mirror for optical surface mount technology","authors":"T. Satoh, A. Ichimura, O. Mikami, S. Tomaru, M. Hikita, T. Uchida","doi":"10.1109/IEMTIM.1998.704535","DOIUrl":"https://doi.org/10.1109/IEMTIM.1998.704535","url":null,"abstract":"Low loss optical waveguides with a 45/spl deg/ micro reflection mirror are the key to optical surface mount technology (O-SMT), which was proposed to provide a possible solution to growing serious problems in opto-electronic product manufacturing processes. This paper presents an experimental and theoretical study of optical coupling between a laser diode placed on a board surface and a polymeric channel waveguide through a micro-mirror. The laser diode applied here has a built-in spot-size converter which enables a narrower beam divergence than conventional laser diodes. It is clarified that the 45/spl deg/ reflection mirror has a useful function of changing the beam direction from the vertical to the horizontal and vice versa, and passive alignment for positioning laser diodes can be applied in O-SMT.","PeriodicalId":260028,"journal":{"name":"2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124411348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
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