Modeling and characterization studies of parasitic elements in lead-on-chip thin-small-outline packaging

Abstract

Parameters affecting the parastic elements of a lead-on-chip (LOC) thin small outline package (TSOP) were studied by modeling with a TI internal RLC extractor and measurement technique using a vector network analyzer (VNA). Variation in the resistance (R), inductance (L) and capacitance (C) of a TSOP with respect to changes in the lead dimensions were assessed by modeling with a line-and-space pattern based on the TSOP geometry. The effect on RLC due to changes in the lead-to-ground separation, electrical properties of the materials and frequency were assessed by modeling based on a 54-pin TSOP applied to 64 Mb/spl times/16 SDRAM. Measurement was made to confirm the frequency dependence of RLC for Alloy42 (A42), copper (Cu) and palladium plated copper (Pd-Cu) as leadframe material. Some fundamentals for packaging design are summarized. For instance, L can be reduced by increasing lead width and decreasing lead-to-ground separation simultaneously. In frequency studies, it is found that the A42 leadframe has a higher frequency dependence on R and L, and is thus electrically inferior to Cu and Pd-Cu leadframes.