Micro/chip scale packages and the semiconductor industry road map

Abstract

Micro/chip scale packages are the hot topic in the IC packaging industry at present, but important questions regarding the fit between advances in IC technology and packaging technology remain unanswered. By exploring the recently published Semiconductor Industry Association (SIA) semiconductor technology road map, some of the answers are forthcoming, particularly with regard to the role of miniaturization of IC packages. In addition to concerns about miniaturization, several materials and process challenges are identified, along with strategies for solution development. Once the challenges of IC packaging are overcome, the next step will require substantial care to avoid raising major entry barriers to the use of these packages. The established design and assembly infrastructure throughout the world cannot adapt overnight to the whims of the IC packager. Thus the challenges of printed wiring board design and fabrication, component handling and placement, attachment methods, etc., must also be addressed. These multidisciplinary considerations provide for two alternative paths to meet the needs of the electronics industry's varied packaging, interconnection and assembly objectives. One path, technological convergence, melds the materials and process requirements of packaging and interconnection. The other path, technology integration, transfers the packaging requirements further down the value delivery chain.