{"title":"Fabrication of low cost microwave circuits and structures using an advanced thick film technology","authors":"P. Barnwell, J. Wood","doi":"10.1109/IEMTIM.1998.704669","DOIUrl":"https://doi.org/10.1109/IEMTIM.1998.704669","url":null,"abstract":"The explosive growth in applications for microwave circuits and systems is demanding new approaches to circuit technology to satisfy system demands. With applications such as phased array antennas, satellite communications and car collision avoidance radar, there is a high volume demand for microwave circuits. Established circuit technologies, primarily thin film, are too high in cost to meet these demands. What is needed is a lower cost technology which still offers high performance. Such a technology is described here. Advanced thick film materials are combined with photoprocessing techniques to provide outstanding circuit performance. Line resolutions of 12 /spl mu/m are available, together with via dimensions of 50 /spl mu/m. The electrical performance of the materials is also excellent, with very high conductivity lines and low loss, low dielectric constant dielectric materials. The paper briefly reviews this technology. The majority of the paper concentrates on describing examples of microwave components and their performance when fabricated using this technology. It is shown that it is possible to equal or even exceed thin film performance at frequencies up to at least 80 GHz using the conductor material on ceramic substrates. Particular attention is paid to novel microwave structures using this technology. A structure referred to as \"microstrip on dielectric\" is illustrated and performance figures are given. Due to the compact form of this structure, small size circuits with low material costs and hence low overall cost result. Test results on components fabricated using this approach are also given.","PeriodicalId":260028,"journal":{"name":"2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133153056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Damage and fracture evaluation in microelectronic assemblies by FEA and experimental investigations","authors":"J. Auersperg, T. Winkler, D. Vogel, B. Michel","doi":"10.1109/IEMTIM.1998.704662","DOIUrl":"https://doi.org/10.1109/IEMTIM.1998.704662","url":null,"abstract":"Thermomechanical reliability of electronic packaging such as flip chip and chip scale packaging is most important for adoption of these technologies in industrial applications. However, various kinds of inhomogeneities, localized stresses and thermal mismatch between several components lead to interface delaminations, chip cracking and solder interconnect fatigue. Nonlinear finite element simulations which respect the nonlinear, temperature and rate dependent behaviour of different materials used (metals, polymeric and solder materials) and experimental investigations have been used for failure analysis. The development and application of failure models (e.g. thermal fatigue, lifetime prediction by Coffin-Manson type equations, integral fracture mechanics approaches such as J-, J/spl circ/-, and /spl Delta/T*-integral, and evaluation of critical regions) is explained. The influence of the scatter of some model parameters is investigated by probabilistic failure concepts. Additionally, simulation of damage growth in solder interconnects by an automatic adaptive finite element technique is performed using inherent local damage models to validate crack and damage models used. Consequently, some results have been compared to micrographs from damaged interconnects and to strain measurement results obtained by the microDAC measurement method. The application of those combined investigations should help further understanding of failure mechanisms especially in solder joints, and should support further applications for enhancing the thermomechanical reliability of advanced electronic assemblies.","PeriodicalId":260028,"journal":{"name":"2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131600047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Electronic packaging research and education in the 21st century at PRC","authors":"R. Tummala","doi":"10.1109/IEMTIM.1998.704561","DOIUrl":"https://doi.org/10.1109/IEMTIM.1998.704561","url":null,"abstract":"The next generation of packaging must be consistent with both semiconductors and systems. The packages in the past have been mostly passive containers for semiconductors. Given the needs for extremely compact and ultra low-cost electronic systems of the 21st century and given the wafer fabrication costs that are $3-5B per plant, this paper looks at what packaging should be in the 21st century. Any packaging technology should also be built upon the learning of current state-of-the-art packaging. Highly integrated and low-cost packaging as a single level and single component that is capable of improving performance, reducing cost and size by about an order of magnitude in each case is proposed. Similar advances are also proposed in electronic packaging education for the 21st century, introducing packaging at pre-college level and providing a system-level view at undergraduate and graduate levels.","PeriodicalId":260028,"journal":{"name":"2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225)","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122052011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A roadmap to low cost flip chip and CSP using electroless Ni/Au","authors":"T. Oppert, E. Zakel, T. Teutsch","doi":"10.1109/IEMTIM.1998.704534","DOIUrl":"https://doi.org/10.1109/IEMTIM.1998.704534","url":null,"abstract":"Flip chip (FC) technology is gaining an increased level of importance for a variety of applications based on flip chip on board or flip chip in package. The first driving force for the introduction of this technology was the need to achieve increased speed and performance along with higher I/O count. A breakthrough, however, will be the use of flip chip due to cost reduction. For this aim, it is essential to use low cost bumping techniques in combination with an SMT-compatible assembly method. The FC techniques presented in this paper are all based on an electroless Ni/Au bumping process which has been developed by TUB/IZM and implemented into production by Pac Tech. This paper shows a roadmap based on electroless nickel/gold bumping for all flip chip interconnection technologies currently used in industry. Also, the roadmap to future developments in the semiconductor industry based on 300 mm wafers and the use of new pad metallisations such as Cu is shown. The compatibility of electroless nickel bumping in particular with these new technologies to be implemented in wafer manufacturing in the next millenium shows that this key technology offers a roadmap to flip chip technology not only for products and wafer technologies in use at present but for next generation wafer technologies. This paper looks at electroless Ni as a basis for anisotropic conductive adhesive (ACF) flip chip assembly, for polymeric flip chip assembly (conductive adhesive) and for soldering and direct chip attach-type applications using different solder alloys.","PeriodicalId":260028,"journal":{"name":"2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122128476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Sumikawa, Yasuyuki Saza, T. Sato, C. Yoshioka, A. Rai, T. Nukii
{"title":"Reliability of soldered joints in CSPs of various designs and mounting conditions","authors":"M. Sumikawa, Yasuyuki Saza, T. Sato, C. Yoshioka, A. Rai, T. Nukii","doi":"10.1109/IEMTIM.1998.704627","DOIUrl":"https://doi.org/10.1109/IEMTIM.1998.704627","url":null,"abstract":"The chip size package (CSP) is in use in various portable electronic products. Further evaluation of the reliability of its soldered joints is required all the more because these soldered joints are invisible. This study focuses on the thermal fatigue life of soldered joints in the CSP. CSPs were mounted on printed circuit boards (PCBs) in various configurations and mounting conditions, and underwent thermal cycle testing. Then, the fatigue lives of their soldered joints were compared. As a result, the following two facts became apparent. Firstly, reflowing at a 210/spl deg/C peak tends to result in failures that may be derived from poor wetting between solder and pad, in cases where the CSP is mounted on a nickel and gold plated pad. Secondly, the solder joint size has a great influence on its fatigue life. The larger the solder joints that were made, the longer fatigue life they indicated. A finite element method (FEM) analysis of these mounted structures was also executed. The viscoplastic (creep and plastic) properties of solder were evaluated to compute the equivalent inelastic strain occurring in the joints. A parameter in the Coffin-Manson equation is obtained from the computed inelastic strain amplitudes and the experimentally obtained fatigue lives. This result enables us to estimate the fatigue life of CSP solder joints without actual tests.","PeriodicalId":260028,"journal":{"name":"2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128920141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Popcorn cracking in a plastic ball grid array package","authors":"T. Shioda, J. Tanaka, A. Hagimura","doi":"10.1109/IEMTIM.1998.704621","DOIUrl":"https://doi.org/10.1109/IEMTIM.1998.704621","url":null,"abstract":"The preconditioning testing (85/spl deg/C/85% RH or 6O% RH/168 hrs) for a plastic ball grid array (PBGA) package was carried out. The use of a substrate with relatively high rigidity at temperatures higher than 200/spl deg/C resulted in improvement of the popcorn cracking resistance during IR reflow. This result was reasonably explained to be due to the relatively large compressive stress between chip and substrate induced by its high rigidity. Further improvement was observed by increasing the thickness of the solder resist (SR) or the Ag-filled die attach (DA) layer.","PeriodicalId":260028,"journal":{"name":"2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225)","volume":"40 11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128167581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Pb-free external lead finishes for electronic components: Tin-bismuth and tin-silver","authors":"R. Schetty","doi":"10.1109/IEMTIM.1998.704707","DOIUrl":"https://doi.org/10.1109/IEMTIM.1998.704707","url":null,"abstract":"While research and development of both Pb-free solder pastes and Pb-free circuit board coatings has been substantial, to date minimal information has been published regarding Pb-free finishes on the external component leads. To create a truly environmentally safe, Pb-free electronic assembly, it is required that Pb-free materials be used throughout the interconnection. While the replacement of tin-lead by nickel/palladium and nickel/palladium/gold coatings does produce a Pb-free component finish which is being used commercially in certain applications at present, this technology is limited to copper alloy base materials. In Japan, an iron/nickel alloy (Alloy 42) is a very common base material for electronic components, and therefore layering systems based on palladium are not a viable alternative for the majority of electronic components in Japan. An external lead finish composed of a Pb-free solder is required which replaces existing tin-lead. To date, most research on Pb-free solder paste materials has identified two binary alloys of tin, tin-bismuth (Sn-Bi) and tin-silver (Sn-Ag), along with ternary and quaternary alloy variations of these, as the most promising for most electronics assembly operations. External lead finishes which are compatible with tin-bismuth and tin-silver solder pastes are therefore required. This paper introduces Sn-Bi and Sn-Ag electroplating processes for external lead finishing applications which satisfy Pb-free finish requirements for the electronics industry.","PeriodicalId":260028,"journal":{"name":"2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125706703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Knudsen, K. E. Howard, J. Braley, D. Magley, H. Yoshida
{"title":"Reliability, performance and economics of thermally enhanced plastic packages","authors":"A. Knudsen, K. E. Howard, J. Braley, D. Magley, H. Yoshida","doi":"10.1109/IEMTIM.1998.704705","DOIUrl":"https://doi.org/10.1109/IEMTIM.1998.704705","url":null,"abstract":"Thermal demands on electronic packages are increasing. Resolving these issues in plastic packaging frequently involves a balance of engineering, performance and cost. Conventional plastic packages exhibit limited thermal performance. Thus, engineering solutions, such as modified lead frames, heat sinks or spreaders, which often involve a significant increase in cost, must be considered in those applications where heat dissipation requirements exceed design capabilities. The use of a novel hydrolytically-stable aluminum nitride filler (SCAN), replacing standard fused silica fillers, in transfer molded plastic packages offers another option. AlN is an inorganic dielectric possessing a thermal conductivity much higher than standard silica fillers. Molding compounds and various device packages based on this powder have been introduced commercially. These packages offer large improvements in thermal performance, comparable to heat spreaders and in some cases, exposed heat slugs: reductions of 25-30% in /spl Theta//sub ja/ and 50% in /spl Theta//sub jc/, respectively are typical. Reliability data, including electrical, thermal, environmental and mechanical properties, measured for QFP and SOIC packages indicate that SCAN-based packages exhibit reliability equivalent to packages molded with standard molding compounds. Perhaps most importantly, these packages may also offer significant cost savings, depending on the specific package type.","PeriodicalId":260028,"journal":{"name":"2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225)","volume":"207 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133357027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"High density, low cost packaging and interconnect technology","authors":"P. Garrou","doi":"10.1109/IEMTIM.1998.704499","DOIUrl":"https://doi.org/10.1109/IEMTIM.1998.704499","url":null,"abstract":"The increase of I/O on chip is driving chip, package and board interconnect schemes to alternative technologies. Area array flip chips and BGAs are beginning to replace peripheral pad limited chips and tight pitch leads on PQFPs. The PWB industry is looking at technologies which form \"microvias\" to handle the interconnection of these high density chip/package formats. New technologies such as large area processing (LAP) and seamless high off chip connectivity (SHOCC) are being developed to meet these needs.","PeriodicalId":260028,"journal":{"name":"2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133663411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Excess low frequency noises in some electronic materials and components","authors":"K. Takagi","doi":"10.1109/IEMTIM.1998.704672","DOIUrl":"https://doi.org/10.1109/IEMTIM.1998.704672","url":null,"abstract":"We devised burst noise eliminating equipment and characterized the 1/f and burst noise in some electronic materials, components, electric contacts and bipolar transistors. The burst-eliminated noise spectrum is the 1/f type. The noise intensity is proportional to the square of the current and to the fifth power of the contact resistance. This contact resistance dependence of the noise is analyzed with the constriction resistance of the contact surface material. The measured results are also shown in the amplitude and phase fluctuations in the transistor collector current. They are also of 1/f type and correlate each other. On the other hand, we did not find this correlation in another transistor with burst noise. Hence, the 1/f fluctuation is considered to be due to diffusion or mobility fluctuation and the burst noise is not due to the diffusion process in the solid.","PeriodicalId":260028,"journal":{"name":"2nd 1998 IEMT/IMC Symposium (IEEE Cat. No.98EX225)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133947955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}