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AlGaN/GaN HEMT Large Signal Nonlinear Compact Model Accounting for Thermal Effects and Trapping Dispersion 考虑热效应和捕获色散的AlGaN/GaN HEMT大信号非线性紧凑模型
2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) Pub Date : 2013-11-11 DOI: 10.1109/CSICS.2013.6659214
Yueying Liu, E. Reese
{"title":"AlGaN/GaN HEMT Large Signal Nonlinear Compact Model Accounting for Thermal Effects and Trapping Dispersion","authors":"Yueying Liu, E. Reese","doi":"10.1109/CSICS.2013.6659214","DOIUrl":"https://doi.org/10.1109/CSICS.2013.6659214","url":null,"abstract":"A customized nonlinear compact model is applied to AlGaN/GaN HEMT devices for Power Amplifier applications. The model formulation is created to represent behavior specific to GaN HEMT devices. The model incorporates novel formulations for Ids equations, bias dependency of access resistances, charge storage, and dispersion models, tailored to GaN HEMT device behavior. The model has been used to generate nonlinear common-source models in frequency ranges of S-, Ku- and Ka-band processes. A typical 4x50um S-band and Ku-band device will be used to demonstrate the extraction and validation of the model, in which the model has predicted the DCIV, CW S Parameters, and LP results accurately.","PeriodicalId":257256,"journal":{"name":"2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114361272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A DFT Loopback Scheme for ADC ENOB Testing Using an All-Digital ATE 使用全数字ATE进行ADC ENOB测试的DFT环回方案
2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) Pub Date : 2013-11-11 DOI: 10.1109/CSICS.2013.6659198
S. Aouini, C. Kurowski, Naim Ben-Hamida, Jean-François Bousquet, D. McPherson, Darren Wadden
{"title":"A DFT Loopback Scheme for ADC ENOB Testing Using an All-Digital ATE","authors":"S. Aouini, C. Kurowski, Naim Ben-Hamida, Jean-François Bousquet, D. McPherson, Darren Wadden","doi":"10.1109/CSICS.2013.6659198","DOIUrl":"https://doi.org/10.1109/CSICS.2013.6659198","url":null,"abstract":"This article presents a design-for-test (DFT) loopback scheme for testing the analog portion of a mixed-signal chip using an all- digital tester. In fact, the proposed approach is used to assess the ENOB of a high-speed 6-bit ADC without the need for an external signal generator. Using an on-chip PLL with a programmable divider, a divided version of the 16GHz clock is passed through an on-chip buffer network where the output driver amplitude is programmable to achieve the desired fill ratio (~80%). The test PLL is coherent to the system PLL as they are driven from the same reference clock; hence, no windowing needs to be applied to the ADC output prior to performing the FFT for ENOB assessment. The on-chip output driver has an open-drain configuration that is far- end terminated through 50Ω pull-up resistors connected to a 2.0V external supply on the device interface board (DIB). The output is then applied to a 5th order external filter on the DIB with a 3dB cutoff frequency of 2.4GHz to filter out the high order harmonics prior to looping back the stimulus to the ADC front-end. The proposed scheme is implemented within a CMOS 32nm ADC macro and is experimentally validated using a commercial all-digital automated-test-equipment (ATE). A 4.5 bit ENOB was experimentally measured using the ADC under test. Unlike conventional loopback schemes, the proposed architecture is not susceptible to fault masking.","PeriodicalId":257256,"journal":{"name":"2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115847681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Low Distortion CATV Power Amplifier Using GaAs HJFET and GaN FET Cascode Distortion Cancellation Technique 采用GaAs HJFET和GaN FET级联失真消除技术的低失真有线电视功率放大器
2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) Pub Date : 2013-11-11 DOI: 10.1109/CSICS.2013.6659236
I. Takenaka, K. Ishikura, Shinnosuke Takahashi, K. Asano, Hidemasa Takahashi, Y. Murase, Y. Ando, Takekatsu Ueki, K. Nakai, Y. Yamaguchi, Y. Kakuta
{"title":"Low Distortion CATV Power Amplifier Using GaAs HJFET and GaN FET Cascode Distortion Cancellation Technique","authors":"I. Takenaka, K. Ishikura, Shinnosuke Takahashi, K. Asano, Hidemasa Takahashi, Y. Murase, Y. Ando, Takekatsu Ueki, K. Nakai, Y. Yamaguchi, Y. Kakuta","doi":"10.1109/CSICS.2013.6659236","DOIUrl":"https://doi.org/10.1109/CSICS.2013.6659236","url":null,"abstract":"We have successfully developed broadband low distortion cable television (CATV) power amplifier with AlGaN/GaN hetero-structure field-effect transistor (HFET) capable of high voltage operation for high output power. To realize low distortion characteristics required for modern CATV system, we investigated low distortion cascode configuration composed of GaAs hetero-junction FET (HJFET) for first stage and GaN FET for final stage. The third-order distortion characteristics were improved by realizing distortion cancellation between GaAs HJFET and GaN FET with optimized transconductance (gm)-profile employing Volterra distortion analysis on load-line based on pulsed I-V characteristics. The developed CATV power amplifier demonstrated, to our knowledge, the lowest composite triple beat (CTB) characteristics less than -72 dBc at low drain current condition of 380 mA under 53.7 dBmV at 865 MHz, 11.7 dB tilt, 132 channels.","PeriodicalId":257256,"journal":{"name":"2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115986280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
More Than Moore: GaN HEMTs and Si CMOS Get It Together 超越摩尔:GaN hemt和Si CMOS结合在一起
2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) Pub Date : 2013-11-11 DOI: 10.1109/CSICS.2013.6659239
T. Kazior, J. LaRoche, W. Hoke
{"title":"More Than Moore: GaN HEMTs and Si CMOS Get It Together","authors":"T. Kazior, J. LaRoche, W. Hoke","doi":"10.1109/CSICS.2013.6659239","DOIUrl":"https://doi.org/10.1109/CSICS.2013.6659239","url":null,"abstract":"Advances in silicon technology continue to revolutionize microelectronics. However, Si cannot do everything and circuits based on other materials systems are required. What is the best way to integrate these dissimilar materials and enhance the capabilities of Si, thereby continuing the microelectronics revolution? In this paper, we summarize our results on the successful integration of GaN HEMTs with Si CMOS on a common silicon substrate using an integration/fabrication process similar to a SiGe BiCMOS process. Our GaN - Si CMOS process is being scaled to 200 mm diameter wafers and integrated with scaled CMOS and used to fabricate RF and mixed signals circuits with on-chip digital control/calibration. Thus, heterogeneous integration of GaN with Si CMOS enables a new class of high performance ICs that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low cost microelectronics for a wide range of applications.","PeriodicalId":257256,"journal":{"name":"2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121395572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
A 3-Vppd 730-mW Linear Driver IC Using InP HBTs for Advanced Optical Modulations 基于InP hbt的3-Vppd 730-mW线性驱动IC用于高级光调制
2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) Pub Date : 2013-11-11 DOI: 10.1109/CSICS.2013.6659193
M. Nagatani, Y. Bouvier, H. Nosaka, K. Murata
{"title":"A 3-Vppd 730-mW Linear Driver IC Using InP HBTs for Advanced Optical Modulations","authors":"M. Nagatani, Y. Bouvier, H. Nosaka, K. Murata","doi":"10.1109/CSICS.2013.6659193","DOIUrl":"https://doi.org/10.1109/CSICS.2013.6659193","url":null,"abstract":"This paper presents a 3-Vppd 730-mW linear optical modulator driver IC for advanced modulations suitable for optical communications systems operating at 100-Gb/b/ch and beyond. The driver was designed and fabricated using 0.5-um-emitter InP HBT technology, which yields a peak ft of 290 GHz, a peak fmax of 320 GHz, and BVceo of approximately 4 V. The linear driver has a two-stage lumped configuration comprising a variable-gain amplifier (VGA) and an output cascode amplifier. It provides linear differential output amplitude of up to 3 Vppd and consumes only 730 mW. It has a large bandwidth of 37.8 GHz and a maximum differential gain of 16.2 dB with 6-dB variable gain range. Total harmonic distortion (THD) is as low as 1.2% at 1 GHz and better than 3.8% up to 16 GHz. The driver provides very clear binary and multilevel output and can be applied to optical transmissions of 100-Gb/s/ch and beyond.","PeriodicalId":257256,"journal":{"name":"2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130801745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
A CMOS SOI Stacked Shunt Switch with Sub-500ps Time Constant and 19-Vpp Breakdown 时间常数低于500ps，击穿19vpp的CMOS SOI堆叠并联开关
2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) Pub Date : 2013-11-11 DOI: 10.1109/CSICS.2013.6659196
Cooper S. Levy, P. Asbeck, J. Buckwalter
{"title":"A CMOS SOI Stacked Shunt Switch with Sub-500ps Time Constant and 19-Vpp Breakdown","authors":"Cooper S. Levy, P. Asbeck, J. Buckwalter","doi":"10.1109/CSICS.2013.6659196","DOIUrl":"https://doi.org/10.1109/CSICS.2013.6659196","url":null,"abstract":"This work demonstrates a shunt stacked-FET switch with both high switching speed (~1ns) and high RF voltage handling capability (30 dBm). A key development in the implementation of this stacked structure is a dynamic gate bias adjustment to track the voltage swing. Measured performance for a shunt capacitor-switch network fabricated in 45-nm CMOS SOI (Leff = 40 nm) is characterized. The switch achieves a RonCoff time constant of less than 500ps, and is shown to handle a 19Vpp RF signal swing. These characteristics enable use in digital dynamic load modulation of power amplifiers at bandwidths above 10 MHz.","PeriodicalId":257256,"journal":{"name":"2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121461795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
An LC VCO for High Power Millimeter-Wave Signal Generation 用于大功率毫米波信号产生的LC压控振荡器
2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) Pub Date : 2013-11-11 DOI: 10.1109/CSICS.2013.6659216
S. Lai, D. Kuylenstierna, R. Kozhuharov, B. Hansson, H. Zirath
{"title":"An LC VCO for High Power Millimeter-Wave Signal Generation","authors":"S. Lai, D. Kuylenstierna, R. Kozhuharov, B. Hansson, H. Zirath","doi":"10.1109/CSICS.2013.6659216","DOIUrl":"https://doi.org/10.1109/CSICS.2013.6659216","url":null,"abstract":"The paper presents a G band second harmonic VCO in 0.25um InP DHBT technology. The VCO uses a cross-coupled topology with a capacitive emitter degeneration and a second order tank to peak second harmonic signal. The VCO presents a tuning range from 169-176GHz and delivers a peak power of -2.7dBm, biased at Vc=4V and Ic=46mA. To the best of authors' knowledge, this is the first HBT cross-coupled VCO designed above 100 GHz.","PeriodicalId":257256,"journal":{"name":"2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"58 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114114077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
230-240 GHz, 30 dB Gain Amplifier in INP-HEMT for Multi-10 Gb/s Data Communication Systems 用于多- 10gb /s数据通信系统的INP-HEMT中230- 240ghz, 30db增益放大器
2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) Pub Date : 2013-11-11 DOI: 10.1109/CSICS.2013.6659181
Y. Kawano, H. Matsumura, S. Shiba, Masaru Sato, Toshihide Suzuki, Y. Nakasha, Tsuyoshi Takahashi, K. Makiyama, N. Hara
{"title":"230-240 GHz, 30 dB Gain Amplifier in INP-HEMT for Multi-10 Gb/s Data Communication Systems","authors":"Y. Kawano, H. Matsumura, S. Shiba, Masaru Sato, Toshihide Suzuki, Y. Nakasha, Tsuyoshi Takahashi, K. Makiyama, N. Hara","doi":"10.1109/CSICS.2013.6659181","DOIUrl":"https://doi.org/10.1109/CSICS.2013.6659181","url":null,"abstract":"In this paper, a multi-stage amplifier in 75-nm InP-HEMT technology is described. To achieve a remarkably high gain in a submillimeter waveband, feedback reduction architectures are proposed. The small signal gain of the fabricated amplifier is 30 dB around 230 GHz, and the 3-dB bandwidth is 228 to 242 GHz. The total power consumption of the amplifier was 130 mW. A modulator and an envelope detector are also implemented in the amplifier to confirm a large signal operation. When 10 Gb/s data is input to modulator, a clear eye-opening waveform from the detector output can be successfully obtained.","PeriodicalId":257256,"journal":{"name":"2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116051044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Electrical and Thermal Performance of AlGaN/GaN HEMTs on Diamond Substrate for RF Applications 金刚石基板上用于射频应用的AlGaN/GaN hemt的电学和热学性能
2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) Pub Date : 2013-11-11 DOI: 10.1109/CSICS.2013.6659225
D. Dumka, T. Chou, J. Jimenez, D. Fanning, D. Francis, F. Faili, F. Ejeckam, M. Bernardoni, J. Pomeroy, Martin Kuball
{"title":"Electrical and Thermal Performance of AlGaN/GaN HEMTs on Diamond Substrate for RF Applications","authors":"D. Dumka, T. Chou, J. Jimenez, D. Fanning, D. Francis, F. Faili, F. Ejeckam, M. Bernardoni, J. Pomeroy, Martin Kuball","doi":"10.1109/CSICS.2013.6659225","DOIUrl":"https://doi.org/10.1109/CSICS.2013.6659225","url":null,"abstract":"Thermal conductivity of the substrate affects the performance of high power RF devices. It is a dominant limiting factor in current state-of- the-art GaN HEMTs on SiC substrate. Due to high thermal conductivity, diamond substrate is an attractive alternative for GaN HEMTs. We have developed device quality GaN-on-diamond wafers using CVD diamond and fabricated 0.25 μm gate length HEMTs. We present detailed electrical and thermal results of the fabricated devices, which show RF power comparable to standard GaN-on-SiC HEMTs. We demonstrate over 25 % lower channel temperature for these devices compared to GaN-on-SiC devices. Electrical results using DC and RF tests and thermal results using IR thermography and micro-Raman spectroscopy are included.","PeriodicalId":257256,"journal":{"name":"2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114777379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 46
Heteroepitaxial Growth and Power Devices Using AlGaN/GaN HEMT on 200 mm Si (111) Substrate 在200 mm Si(111)衬底上使用AlGaN/GaN HEMT的异质外延生长和功率器件
2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) Pub Date : 2013-11-11 DOI: 10.1109/CSICS.2013.6659231
T. Egawa
{"title":"Heteroepitaxial Growth and Power Devices Using AlGaN/GaN HEMT on 200 mm Si (111) Substrate","authors":"T. Egawa","doi":"10.1109/CSICS.2013.6659231","DOIUrl":"https://doi.org/10.1109/CSICS.2013.6659231","url":null,"abstract":"Developments of heteroepitaxial growth and characteristics of MOCVD-grown AlGaN/GaN HEMTs on Si substrates are presented. High-temperature-grown AlGaN/AlN intermediate layers and GaN/AlN strained layer superlattice are effective in improving the crystal quality of a following GaN layer and in growing thick device structure on Si. The AlGaN/GaN HEMT has been successfully grown on 8-inch Si, which indicates that the gas phase reaction is minimized in this growth. The device exhibited the excellent uniformity, the 2DEG properties and the device characteristics.","PeriodicalId":257256,"journal":{"name":"2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125851198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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