时间常数低于500ps,击穿19vpp的CMOS SOI堆叠并联开关

Cooper S. Levy, P. Asbeck, J. Buckwalter
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引用次数: 11

摘要

本工作演示了一种具有高开关速度(~1ns)和高射频电压处理能力(30dbm)的并联堆叠fet开关。实现这种堆叠结构的一个关键发展是动态栅极偏置调整,以跟踪电压摆动。对45 nm (Leff = 40 nm) CMOS SOI制程的并联电容开关网络进行了性能测试。该开关实现了小于500ps的RonCoff时间常数,并显示可以处理19Vpp的RF信号摆动。这些特性可用于带宽在10mhz以上的功率放大器的数字动态负载调制。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A CMOS SOI Stacked Shunt Switch with Sub-500ps Time Constant and 19-Vpp Breakdown
This work demonstrates a shunt stacked-FET switch with both high switching speed (~1ns) and high RF voltage handling capability (30 dBm). A key development in the implementation of this stacked structure is a dynamic gate bias adjustment to track the voltage swing. Measured performance for a shunt capacitor-switch network fabricated in 45-nm CMOS SOI (Leff = 40 nm) is characterized. The switch achieves a RonCoff time constant of less than 500ps, and is shown to handle a 19Vpp RF signal swing. These characteristics enable use in digital dynamic load modulation of power amplifiers at bandwidths above 10 MHz.
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