{"title":"时间常数低于500ps,击穿19vpp的CMOS SOI堆叠并联开关","authors":"Cooper S. Levy, P. Asbeck, J. Buckwalter","doi":"10.1109/CSICS.2013.6659196","DOIUrl":null,"url":null,"abstract":"This work demonstrates a shunt stacked-FET switch with both high switching speed (~1ns) and high RF voltage handling capability (30 dBm). A key development in the implementation of this stacked structure is a dynamic gate bias adjustment to track the voltage swing. Measured performance for a shunt capacitor-switch network fabricated in 45-nm CMOS SOI (Leff = 40 nm) is characterized. The switch achieves a RonCoff time constant of less than 500ps, and is shown to handle a 19Vpp RF signal swing. These characteristics enable use in digital dynamic load modulation of power amplifiers at bandwidths above 10 MHz.","PeriodicalId":257256,"journal":{"name":"2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"A CMOS SOI Stacked Shunt Switch with Sub-500ps Time Constant and 19-Vpp Breakdown\",\"authors\":\"Cooper S. Levy, P. Asbeck, J. Buckwalter\",\"doi\":\"10.1109/CSICS.2013.6659196\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This work demonstrates a shunt stacked-FET switch with both high switching speed (~1ns) and high RF voltage handling capability (30 dBm). A key development in the implementation of this stacked structure is a dynamic gate bias adjustment to track the voltage swing. Measured performance for a shunt capacitor-switch network fabricated in 45-nm CMOS SOI (Leff = 40 nm) is characterized. The switch achieves a RonCoff time constant of less than 500ps, and is shown to handle a 19Vpp RF signal swing. These characteristics enable use in digital dynamic load modulation of power amplifiers at bandwidths above 10 MHz.\",\"PeriodicalId\":257256,\"journal\":{\"name\":\"2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)\",\"volume\":\"97 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-11-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CSICS.2013.6659196\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CSICS.2013.6659196","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A CMOS SOI Stacked Shunt Switch with Sub-500ps Time Constant and 19-Vpp Breakdown
This work demonstrates a shunt stacked-FET switch with both high switching speed (~1ns) and high RF voltage handling capability (30 dBm). A key development in the implementation of this stacked structure is a dynamic gate bias adjustment to track the voltage swing. Measured performance for a shunt capacitor-switch network fabricated in 45-nm CMOS SOI (Leff = 40 nm) is characterized. The switch achieves a RonCoff time constant of less than 500ps, and is shown to handle a 19Vpp RF signal swing. These characteristics enable use in digital dynamic load modulation of power amplifiers at bandwidths above 10 MHz.