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A Low-Spurious E-Band GaAs MMIC Frequency Converter for Over-Gbps Wireless Communication 一种用于超gbps无线通信的低杂散e带GaAs MMIC变频器
2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) Pub Date : 2013-11-11 DOI: 10.1109/CSICS.2013.6659202
Yasuhiro Morita, S. Kishimoto, M. Ito, K. Motoi, K. Kunihiro
{"title":"A Low-Spurious E-Band GaAs MMIC Frequency Converter for Over-Gbps Wireless Communication","authors":"Yasuhiro Morita, S. Kishimoto, M. Ito, K. Motoi, K. Kunihiro","doi":"10.1109/CSICS.2013.6659202","DOIUrl":"https://doi.org/10.1109/CSICS.2013.6659202","url":null,"abstract":"A highly integrated, low-spurious E-band MMIC frequency converter, which comprises a sub-harmonic mixer with an LO multiplier and a carrier driver, is presented. An APDP (Anti-Parallel Diode Pair) is used to the mixer and the multiplier so as to prevent a carrier leakage and the 2nd harmonic of an input LO, respectively. Several filters are also applied to suppress some spurious signals from the circuits. An MMIC is fabricated in 0.13um GaAs pHEMT technology, and measurement results show that a ratio between the desired carrier and the other spurious signals is as high as > 50 dB, and that the mixer has conversion loss of <; 12 dB and carrier-RF isolation of > 51 dB. Furthermore, the fabricated MMIC is applied to E-band equipment, where 1.2Gbps 64QAM wireless communication with 250MHz bandwidth (spectral efficiency of 4.8 bit/s/Hz) is achieved.","PeriodicalId":257256,"journal":{"name":"2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121348548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Novel Technique for GaN HEMT Trap States Characterisation GaN HEMT阱态表征新技术
2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) Pub Date : 2013-11-11 DOI: 10.1109/CSICS.2013.6659205
P. Wright, M. Thorsell
{"title":"A Novel Technique for GaN HEMT Trap States Characterisation","authors":"P. Wright, M. Thorsell","doi":"10.1109/CSICS.2013.6659205","DOIUrl":"https://doi.org/10.1109/CSICS.2013.6659205","url":null,"abstract":"A newly investigated measurement approach to analysing the effects of long-term memory effects in wide band-gap semiconductor radio-frequency (RF) transistors is presented. This approach utilises a combination of hybrid-active load-pull and time-domain waveform measurement analysis, whilst adopting a novel measurement technique for initiating charge trapping-based transients in a gallium nitride (GaN) HEMT transistor. Switching actively between two load impedances with theoretically common power amplifier (PA) performance characteristics, a step function in the dynamic drain-voltage (vd) is initiated, whilst minimising gate-voltage and average drain-current variation. In isolating the step function to the drain side of the device only it is possible to extract dependencies of the RF drain-voltage on trap states in the transistor such as those that may occur when subjected to dynamic traffic in in-the-field applications. The measurement technique has shown the potential for extracting both time-constant and charge-trapping magnitude parameters for comparison with traditional pulse-IV characterisations for the purpose of modelling memory in GaN transistors.","PeriodicalId":257256,"journal":{"name":"2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121372817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Frequency Dispersion of Drain Conductance in AlGaN/GaN HEMT Evaluated Using Sinusoidal Wave Signal Input 用正弦波信号输入评价AlGaN/GaN HEMT漏极电导的频散特性
2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) Pub Date : 2013-11-11 DOI: 10.1109/CSICS.2013.6659227
A. Wakejima, Takashi Yamada, T. Narita, A. Ando, T. Egawa
{"title":"Frequency Dispersion of Drain Conductance in AlGaN/GaN HEMT Evaluated Using Sinusoidal Wave Signal Input","authors":"A. Wakejima, Takashi Yamada, T. Narita, A. Ando, T. Egawa","doi":"10.1109/CSICS.2013.6659227","DOIUrl":"https://doi.org/10.1109/CSICS.2013.6659227","url":null,"abstract":"We firstly demonstrate dynamic change in a drain conductance of an AlGaN/GaN HEMT from DC to high frequency using sinusoidal wave input signal from a network analyzer which can sweep from hertz to giga hertz. Prior to measurements, a bias-T which is adaptable at a frequency of hertz to mega hertz has been developed. S-parameter measurements sweeping from 5 Hz to 3 GHz reveals that the magnitude of S22 significantly decreases at a hertz to mega hertz frequency range although the phase of S22 is negligibly stable. Also, it is found that the drain conductance evaluated from drain I-V characteristics and that extracted from S- parameters at 100 Hz are comparable and that a drain conductance from mega hertz to hundreds mega hertz is stable, indicating that some trapping or de-trapping effects occur at this frequency range.","PeriodicalId":257256,"journal":{"name":"2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116454584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 32-nm CMOS Frequency Locked Loop for 20-GHz Synthesis with ± 7.6 ppm Resolution 32纳米CMOS锁频环，用于20 ghz合成，分辨率为±7.6 ppm
2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) Pub Date : 2013-11-11 DOI: 10.1109/CSICS.2013.6659192
Jean-François Bousquet, S. Aouini, Naim Ben-Hamida, J. Wolczanski
{"title":"A 32-nm CMOS Frequency Locked Loop for 20-GHz Synthesis with ± 7.6 ppm Resolution","authors":"Jean-François Bousquet, S. Aouini, Naim Ben-Hamida, J. Wolczanski","doi":"10.1109/CSICS.2013.6659192","DOIUrl":"https://doi.org/10.1109/CSICS.2013.6659192","url":null,"abstract":"In this work, a digitally assisted frequency locked loop is implemented using 32-nm CMOS technology and acts as a 20-GHz frequency synthesizer. The frequency difference between the reference clock and the VCO output is obtained using a pair of 18- bit counters. Also, an offset value is added to the counter output to tune the VCO frequency in closed loop. The frequency synthesizer resolution is ± 7.6 p.p.m. over a measured locking range equal to 300 MHz.","PeriodicalId":257256,"journal":{"name":"2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130467609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Multiband and Wide Dynamic Range Digital Polar Transmitter Using Current-Mode Class-D CMOS Power Amplifier 采用电流模式d类CMOS功率放大器的多频带宽动态范围数字极变送器
2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) Pub Date : 2013-11-11 DOI: 10.1109/CSICS.2013.6659240
T. Nakatani, D. Kimball, P. Asbeck
{"title":"Multiband and Wide Dynamic Range Digital Polar Transmitter Using Current-Mode Class-D CMOS Power Amplifier","authors":"T. Nakatani, D. Kimball, P. Asbeck","doi":"10.1109/CSICS.2013.6659240","DOIUrl":"https://doi.org/10.1109/CSICS.2013.6659240","url":null,"abstract":"Techniques are demonstrated to extend the power control dynamic range of a digitally-driven 0.15 um CMOS polar power amplifier to the degree needed for WCDMA handset applications. The output frequency can be tuned over the 0.75-2GHz range, using an on-chip band-switching resonator, and output power of 27-29 dBm is attained. By partitioning the switching PA into multiple 3-state unit cells, power dynamic ranges of 91 / 85 dB are achieved at 0.85 / 1.75 GHz while maintaining high efficiency. By introducing a buck converter that can act not only with pulse width modulation but also in charge sampling mode, the overall DC power consumption in the power back- off regime can be reduced by a factor of approximately 0.7.","PeriodicalId":257256,"journal":{"name":"2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132277476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 60MHz Bandwidth High Efficiency X-Band Envelope Tracking Power Amplifier 60MHz带宽高效率x波段包络跟踪功率放大器
2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) Pub Date : 2013-11-11 DOI: 10.1109/CSICS.2013.6659194
P. Theilmann, Jonmei J. Yan, Cuong Vu, J. Moon, H. Moyer, D. Kimball
{"title":"A 60MHz Bandwidth High Efficiency X-Band Envelope Tracking Power Amplifier","authors":"P. Theilmann, Jonmei J. Yan, Cuong Vu, J. Moon, H. Moyer, D. Kimball","doi":"10.1109/CSICS.2013.6659194","DOIUrl":"https://doi.org/10.1109/CSICS.2013.6659194","url":null,"abstract":"This paper presents a high efficiency X-band envelope-tracking power amplifier (PA) that achieves a 60MHz modulation bandwidth. The system consists of a wideband envelope modulator and a single-chip gallium- nitride (GaN) MMIC X-band PA. The envelope modulator achieves >70% efficiency while delivering >7W into an 8Ω resistive load for a 60MHz LTE-A modulated signal with a 6.6dB PAPR. The envelope tracking system attains a PAE of 35.3% (including the power dissipation of the envelope modulator) with 1.1W of average output power at 9.23GHz using a 20MHz LTE signal. The X-band PA itself was measured to achieve a drain efficiency of 81.6% with a gain of 7.6dB under these conditions.","PeriodicalId":257256,"journal":{"name":"2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122125638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Advances in High-Speed DACs, ADCs, and DSP for Software Defined Optical Modems 软件定义光调制解调器的高速dac、adc和DSP研究进展
2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) Pub Date : 2013-11-11 DOI: 10.1109/CSICS.2013.6659213
C. Laperle, Naim Ben-Hamida, M. O'sullivan
{"title":"Advances in High-Speed DACs, ADCs, and DSP for Software Defined Optical Modems","authors":"C. Laperle, Naim Ben-Hamida, M. O'sullivan","doi":"10.1109/CSICS.2013.6659213","DOIUrl":"https://doi.org/10.1109/CSICS.2013.6659213","url":null,"abstract":"We review digital-to-analog and analog-to-digital converters (DACs and ADCs), as well as digital signal processing (DSP) functions for software defined optical modems using rich modulation formats. These next generation optical transceivers will enable bit rates from 100 Gb/s to 400 Gb/s and 1 Tb/s.","PeriodicalId":257256,"journal":{"name":"2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116816597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A Geometry Scalable Approach to InP HBT Compact Modeling for mm-Wave Applications 一种用于毫米波应用的InP HBT紧凑建模的几何可扩展方法
2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) Pub Date : 2013-11-11 DOI: 10.1109/CSICS.2013.6659200
T. Nardmann, P. Sakalas, Frank Chen, T. Rosenbaum, M. Schroter
{"title":"A Geometry Scalable Approach to InP HBT Compact Modeling for mm-Wave Applications","authors":"T. Nardmann, P. Sakalas, Frank Chen, T. Rosenbaum, M. Schroter","doi":"10.1109/CSICS.2013.6659200","DOIUrl":"https://doi.org/10.1109/CSICS.2013.6659200","url":null,"abstract":"The bias and frequency dependent scaling of InP/InGaAs HBTs with emitter width (and length) has been investigated for a 300GHz foundry process. It was found that the currents, capacitances and resistances related to the emitter dimensions scale quite well. This allows the use of special test structures in combination with geometry variations to distinguish different physical effects and to accurately determine the external elements of the transistor as well as the thermal resistance independently of each other. The approach enables the generation of a geometry scalable set of HICUM/L2 model parameters for a large geometry range. The model was compared to experimental DC, AC and large-signal data of devices with different emitter geometry. The good agreement offers a much wider range of options for optimizing high-speed InP circuits.","PeriodicalId":257256,"journal":{"name":"2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126135087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Tunnel Transistors for Low Power Logic 用于低功耗逻辑的隧道晶体管
2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) Pub Date : 2013-11-11 DOI: 10.1109/CSICS.2013.6659248
S. Datta, R. Bijesh, H. Liu, D. Mohata, V. Narayanan
{"title":"Tunnel Transistors for Low Power Logic","authors":"S. Datta, R. Bijesh, H. Liu, D. Mohata, V. Narayanan","doi":"10.1109/CSICS.2013.6659248","DOIUrl":"https://doi.org/10.1109/CSICS.2013.6659248","url":null,"abstract":"Tunnel transistor (TFET) as steep slope device to enable supply voltage scaling is explored at the device level as well as circuit level. Hetero-junction TFET is demonstrated with high drive current and high on-off current ratio. Hetero-junction TFETs with scaled device geometry outperform Si FINFET at Vcc <; 0.3V. Design considerations of TFET based circuits for logic applications are investigated and performance benchmarked with Si FinFET technology.","PeriodicalId":257256,"journal":{"name":"2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128300752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
Advanced RF IV Waveform Engineering Tool for Use in Device Technology Optimization: RF Pulsed Fully Active Harmonic Load Pull with Synchronized 3eV Laser 先进的射频波形工程工具，用于设备技术优化:射频脉冲全有源谐波负载拉同步3eV激光
2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) Pub Date : 2013-11-11 DOI: 10.1109/CSICS.2013.6659212
M. Casbon, P. Tasker, Wei-Chou Wang, Che-Kai Lin, Wen-Kai Wang, W. Wohlmuth
{"title":"Advanced RF IV Waveform Engineering Tool for Use in Device Technology Optimization: RF Pulsed Fully Active Harmonic Load Pull with Synchronized 3eV Laser","authors":"M. Casbon, P. Tasker, Wei-Chou Wang, Che-Kai Lin, Wen-Kai Wang, W. Wohlmuth","doi":"10.1109/CSICS.2013.6659212","DOIUrl":"https://doi.org/10.1109/CSICS.2013.6659212","url":null,"abstract":"The RF performance obtainable from a device often falls short of the expectations raised by analysis of the DCIV curves. This difference is typically associated with thermal or trapping effects. Hence, RF performance is traditionally assessed using load pull techniques, which can identify the optimum operating conditions, but cannot explain the shortfall. It has previously been shown that RF IV Waveform Engineering methods can give more insight to why there are differences without necessarily identifying their cause [1]. Here we show how adding RF pulse capability can help identify thermal contributions, and a synchronized 3eV Laser excitation can help identify and clear trapping contributions. Together these methods provide a powerful diagnostic tool for device technology optimization.","PeriodicalId":257256,"journal":{"name":"2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125639079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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