Jean-François Bousquet, S. Aouini, Naim Ben-Hamida, J. Wolczanski
{"title":"32纳米CMOS锁频环，用于20 ghz合成，分辨率为±7.6 ppm","authors":"Jean-François Bousquet, S. Aouini, Naim Ben-Hamida, J. Wolczanski","doi":"10.1109/CSICS.2013.6659192","DOIUrl":null,"url":null,"abstract":"In this work, a digitally assisted frequency locked loop is implemented using 32-nm CMOS technology and acts as a 20-GHz frequency synthesizer. The frequency difference between the reference clock and the VCO output is obtained using a pair of 18- bit counters. Also, an offset value is added to the counter output to tune the VCO frequency in closed loop. The frequency synthesizer resolution is ± 7.6 p.p.m. over a measured locking range equal to 300 MHz.","PeriodicalId":257256,"journal":{"name":"2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A 32-nm CMOS Frequency Locked Loop for 20-GHz Synthesis with ± 7.6 ppm Resolution\",\"authors\":\"Jean-François Bousquet, S. Aouini, Naim Ben-Hamida, J. Wolczanski\",\"doi\":\"10.1109/CSICS.2013.6659192\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this work, a digitally assisted frequency locked loop is implemented using 32-nm CMOS technology and acts as a 20-GHz frequency synthesizer. The frequency difference between the reference clock and the VCO output is obtained using a pair of 18- bit counters. Also, an offset value is added to the counter output to tune the VCO frequency in closed loop. The frequency synthesizer resolution is ± 7.6 p.p.m. over a measured locking range equal to 300 MHz.\",\"PeriodicalId\":257256,\"journal\":{\"name\":\"2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-11-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CSICS.2013.6659192\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CSICS.2013.6659192","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 32-nm CMOS Frequency Locked Loop for 20-GHz Synthesis with ± 7.6 ppm Resolution
In this work, a digitally assisted frequency locked loop is implemented using 32-nm CMOS technology and acts as a 20-GHz frequency synthesizer. The frequency difference between the reference clock and the VCO output is obtained using a pair of 18- bit counters. Also, an offset value is added to the counter output to tune the VCO frequency in closed loop. The frequency synthesizer resolution is ± 7.6 p.p.m. over a measured locking range equal to 300 MHz.
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