2009 11th Electronics Packaging Technology Conference最新文献

{"title":"Characterization of DAF tape for embedded micro wafer level packaging","authors":"S. L. Pei-Siang, G. Sharma, Aditya Kumar, V. S. Rao, V. Sheng","doi":"10.1109/EPTC.2009.5416548","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416548","url":null,"abstract":"The requirements of new packaging technologies for smaller, thinner and lighter electronics products have resulted in electronics industry moving towards wafer level packaging. Some of the main advantages of wafer level packaging are suitability for very fine pitch interconnection, low assembly cost and smaller form factor. This is because the package formed through wafer level technology has the same size as the die itself. Wafer level packaging is in demand especially for portable products such as mobile phone and digital camera. With wafers thinned to 100µm, conventional die attach process may not be suitable as the control of bleed out of the die attached paste becomes critical. New generation of die attach material such as the Dicing Die attach film (DDAF) is introduced to control the paste bleed at the die edge as well as to have a consistent bondline thickness. This paper presents the results of DDAF tape lamination on 100µm thin wafer, DDAF tape dicing process characterization and materials characterization in terms of die shear test of 2 DDAF tapes after die attach process and after subjecting to Moisture Sensitivity test Level 3. A three-factor D.O.E (bonding pressure, bonding temperature and bonding time) adopted to understand the dominant contributing factors on DDAF tape bonding process and to understand the effects of bonding parameters on the DDAF bondline thickness and DDAF voids (Table 1). The 3 selected bond forces range from 0.5kg to 2.5kg. Reliability of the DDAF assembly will also be studied and reported in this work.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124419037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Bottom-up filling of Through Silicon Via (TSV) with Parylene as sidewall protection layer","authors":"M. Miao, Yunhui Zhu, Ming Ji, Shengli Ma, Xin Sun, Yufeng Jin","doi":"10.1109/EPTC.2009.5416507","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416507","url":null,"abstract":"In this paper, we present our recent advances in streamlining via-last TSV process flow. Parylene deposition, which is of excellent conformability to the substrate landscape, was introduced into TSV blind via filling process to realize uniform sidewall protection. Simulation was made to analyze the impacts of Parylene sidewall on the electric field distribution inside a blind via with high aspect ratios during electroplating, which indicates that a uniform plating current density distribution may be achieved with the help of the Parylene sidewall, and thus a void-free filling can be guaranteed. Then in experimental microfabrication runs, with Parylene sidewall protection, we achieved bottom-up filling of blind TSV of large ratio aspect at a higher rate. Besides, during our experiments, a “bottom-up plus non-bottom-up” filling methodology is proposed and the microfabrication trials demonstrate its potential capability of filling TSV blind via at a much higher rate.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124558802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High frequency characterization of through silicon via structure","authors":"Khoo Yee Mong, Chua Eng Kee, Lim Teck Guan, Liu Enxiao","doi":"10.1109/EPTC.2009.5416491","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416491","url":null,"abstract":"In 3D package, through silicon via (TSV) have been used to achieve smaller size, better performance stacked package. However to effectively utilize TSV for high frequency package design, the high frequency performance of TSV structure has to be precisely characterized. In this work, a method that allows the high frequency extraction of TSV's S-parameter is presented. Extraction is basically done by using a number of line test structures and back-to-back via-line-via structures. This method of extraction does away with the need to perform probing both on top and below the wafer and thus do not require the use of high cost and complex probe station setup.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"234 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114260961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Achieving high workability in high-end package by controlling microstructure of 4N Cu wire","authors":"S.H. Kim, J. Park, N. Kim, H. Park, J. Moon","doi":"10.1109/EPTC.2009.5416521","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416521","url":null,"abstract":"Nowadays, due to the increment in Gold prices, Copper wire is considered as a low cost material for use in various package groups. Some packages, with a low-pin count of thick size wire, have already succeeded in mass production using Copper wire. In addition, Copper wire has been applied in high-end packages such as BGA, QFP and QFN in small masses, and that production volume is feasible. However, the applications for Copper wire require different conditions from those of Gold wire, due to differences in basic characteristics, such as hardness or the tail breaking force of each metal. These characteristics are a barrier delaying the universal application of Copper wire to the same degree as Gold wire. The main barrier to Copper wire application is 1st bonding problem, for example metal off or pad cratering, and low 2nd workability resulting from frequent bonding errors such as short tail or NSOL(Non Stick on Lead). Therefore, the purpose of this study is to identify methods for hardness reduction and improvements in 2nd workability to solve the application limitations of Copper wire through wire improvement. Our results identified, firstly for FAB(Free Air Ball) or bonded ball hardness for Copper wire, the optimum composition and content to reduce hardness. In addition, regarding the low 2nd workability, the Copper wire tail bond has a lower value and bigger deviation than Gold wire in bondability between the Copper wire and the 2nd lead. To improve this, a study has been conducted on controlling wire manufacturing processes and alloy composition to dramatically increase uniformity of microstructure. Fine and uniform grains of Copper wire were achieved by microstructure control to minimize the quality gap in the product. Furthermore, it is helpful to reduce bonding errors during the 2nd bond, resulting from wire grain uniformity. We have revealed that improvements in Copper wire show increased workability and stable bonding performance, when tested on QFN, QFP and BGA.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130741835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Evaluating the effects of electromigration by using adjustable solder joints of concave shape","authors":"J. Jaeschke, J. Kleff, W. Muller, N. Nissen, H. Reichl","doi":"10.1109/EPTC.2009.5416514","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416514","url":null,"abstract":"Further miniaturization of electronic systems is approaching new limits due to the failure mechanism of electromigration. Electromigration results in a transport of material in solder joints subjected to high electrical current densities. This decreases the system reliability and, therefore, it is necessary to assess and quantify this failure mechanism in solder joints. In this paper we discuss the development of new test structures based on modified flip chip structures, which allow monitoring of electromigration effects in lead-free solder joints. The structures are of concave shape which permits shifting of the failure region within the solder joint into a position suitable for deterministic assessment. For example it thus becomes possible to create a nearly homogeneous distribution of current density in the local failure region remote from interfering Inter-Metallic Compounds (IMCs) and material interfaces. Moreover, a smaller electric current is required to reach high current densities, so that Joule heating decreases. As a result the effects of overlying failure mechanisms are reduced to two main factors of influence, namely current density and temperature. Experiments using SnAg3.5 solder joints have been conducted at temperatures from 100°C to 150°C and current densities from 104 A/cm2 to 7.7×104 A/cm2. Joule heating is evaluated by finite element analysis (FEA) and measured during experiment. The activation energy is found to be 1.32 eV. A scanning electron microscope (SEM) is used to analyze failure characteristics of the structures and a direct comparison of the impacts of electromigration and thermomigration is performed. The results demonstrate the advantages mentioned before and qualify the structures for electromigration research.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130987418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Electrochemical migration study of fine pitch lead free micro bump interconnect","authors":"Daquan Yu, T. Chai, M. L. Thew, Y. Y. Ong","doi":"10.1109/EPTC.2009.5416517","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416517","url":null,"abstract":"Elelctrochemical migration (ECM) test was conducted for fine pitch flip-chip micro bump interconnect. Two kinds of micro bump. i. e., Cu post with SnAg solder and Cu under bump metallization (UBM) with SnAg solder bumps in 50 and 100 µm pitch with non clean flux were used for chip interconnection. The test was conducted under 85ºC/85H condition with various biases. The results indicated that for micro bump with underfill, test with different bias and pitch showed that the smaller the pitch, the higher the bias, the easier for insulation resistance (IR) value drop. By top-down grinding, dendrites were detected and the main compositions of the dendrites were Cu and Sn. The ECM tests confirmed that even with underfill, ECM failure is a concern for micro bump interconnects with fine pitch down to 50 µm. The mechanism of the dendrite formation was proposed and it was believed that the adsorption of water steam by underfill materials and the existence of residual flux were the main reasons for the dendrites formation.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131089512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Adsorbed contamination on ceramic surfaces stored in industrial ambient conditions and its effect on epoxy bleed","authors":"O. Williams, C. Liu, D. P. Webb, P. Firth","doi":"10.1109/EPTC.2009.5416497","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416497","url":null,"abstract":"Maintaining cleanliness of substrates for assembly in optoelectronic modules is important where surfaces will be subjected to further processes in which the surface properties can affect performance. Cleanliness is counter productive when considering epoxy bleed, since the carbon based contamination of surfaces has been seen to reduce surface free energy and inhibit the spread of epoxy material. The origin of this contamination can be from a number of sources including atmosphere, handling, surface treatments and outgassing from storage media. Whilst allowing contamination to remain on the surface can be an effective means of controlling the epoxy bleed, it is not a reliable solution through lack of controllability. Identifying and quantifying this contamination will be a useful step towards the understanding and control of epoxy bleed, whilst its removal will homogenise all surfaces allowing controllable solutions to be implemented. The substrate materials of interest were aluminium oxide and aluminium nitride, which are commonly used in the optoelectronics industry. Storage methods used in industry were recreated for the purpose of this study with storage of samples in tin foil used for comparison. Samples were stored in commercial polymer waffle packs in a variety of atmospheres which they might experience in industry, on an industrial site, for one month. XPS measurements were made following storage to identify the composition of the contamination and its source. Both the degree of carbon contamination and the functional groups of any adsorbed species are known to affect surface energy and epoxy bleed. Therefore narrow band XPS spectra for carbon were analysed for all samples. Of the many methods which could be employed to remove the surface contamination, solvent, plasma cleaning and firing were chosen for their suitability and due to their availability to industry. XPS was performed on samples following cleaning. It was found that the composition of the contamination on the surfaces was not linked to their storage method but the quantity of contamination was. Storing ceramics in polymer waffle packs does not protect them from build up of carbon contamination regardless of storage atmosphere. The use of tin foil for storage can reduce the degree of contamination presence significantly, but not prevent build up entirely. A high degree of bleed was seen in both samples cleaned but not stored as well as in samples cleaned after storage, showing the effects of storage contamination are easily reversed. While storing ceramics for an extended period of time will allow build up of sufficient contamination to stop bleed occurring, samples fresh from suppliers will not have built up sufficient contamination to reduce the surface free energy to a degree such that bleed will not occur.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131419773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"EMI reducing solution by modify EBG structure for stacked packaging","authors":"F. Chang, Kuan-Wen Cheng, S. Wu","doi":"10.1109/EPTC.2009.5416493","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416493","url":null,"abstract":"In this paper, we investigated the Electromagnetic Bandgap structure (EBG) is embedded in a multi-layer board to mitigate EMI in an adjacent board. The design of the new EBG structure proposed here relies on the modification of thin lines and patches. The thin lines serve to provide the equivalent inductances. Simulation results can suppress any frequency band noise effectively.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131183145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Temporary bonding for Chips In Wafer processing","authors":"J. Souriau, A. Jouve, N. Sillon","doi":"10.1109/EPTC.2009.5416513","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416513","url":null,"abstract":"Chip In Wafer is a very challenging concept because this solution allows wafer scale processes for System in Package and a very high miniaturization and performance level. This paper describes a technologies developed for Chip integration In Wafer (CIW). The approach consists in reconstituting a wafer from heterogeneous chips embedded in a resin with the active sides coplanar. This paper present the development of a new process using wafer substrate including alignment marks and a transparence adhesive which allow an accurate dies positioning and holding during the polymer molding. The process presented in this paper is compatible for chips in polymer wafer, chips in silicon wafer, chips in glass wafer and some other frame.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131189412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Improving package assembly process yield for complex high density flip chip applications","authors":"V. Solberg, V. Oganesian","doi":"10.1109/EPTC.2009.5416579","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416579","url":null,"abstract":"The more advanced microprocessor and ASIC semiconductor packaging currently require several thousand I/O contacts and they are expected to expand contact I/O by 30% in the very near future. Consistent die-to-substrate interface, however, remains the most critical barrier in achieving optimum assembly process yield. Semiconductor suppliers have abandoned the traditional wirebond package assembly for many of these higher I/O products, opting for the more compact die face-down flip-chip attachment methodology. This face-down, direct attachment method significantly reduces the semiconductors package size as well as enhancing product performance. While wire-bond interface may remain the preference for many applications, face-down direct chip attachment has gained popularity for the higher-speed processor and ASIC products. There are a number of factors to consider when selecting an optimal semiconductor package configuration for the newer generations of high density controllers and processors; I/O requirement, package footprint, form factor, thermal dissipation, electrical performance, and cost. This paper will describe a new interconnect solution developed to provide a very uniform array of raised solid copper contact features integrated onto the substrate interposer for mounting very fine pitch bumped flip-chip semiconductor die. This unique raised contact substrate enables semiconductor developers to significantly reduce contact pitch on the die without reducing pad size. Solder bumped die are placed directly onto the raised contact features eliminating the need for solder printing on the package substrate. Mounting the bumped die element on this planer topography solves fundamental issues associated with electro-migration and avoids many of the current assembly process related defects. This is because the raised contact features provide a uniform package interconnect that furnishes a consistent standoff height for improving underfill flow control even with low melt solders.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126896626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}