2009 11th Electronics Packaging Technology Conference最新文献_第10页

Experimental studies of the temperature dependence of mechanical solder material properties using nanoindentation 基于纳米压痕的机械焊料性能温度依赖性实验研究

2009 11th Electronics Packaging Technology Conference Pub Date : 2009-12-01 DOI: 10.1109/EPTC.2009.5416573

W. Muller, H. Worrack

{"title":"Experimental studies of the temperature dependence of mechanical solder material properties using nanoindentation","authors":"W. Muller, H. Worrack","doi":"10.1109/EPTC.2009.5416573","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416573","url":null,"abstract":"Microelectronic components are subjected to a continuous miniaturization process. These efforts of a modern electronic industry require quantitative knowledge of the solder material properties in order to guarantee the reliability of the joining process. Of particular interest are the values of Young's modulus and hardness. Corresponding to the small-size of microelectronic devices is required to use adequately sized specimens and miniature tests. In these studies nanoindentation is applied to determine the material properties of Sn91Zn9 and Sn42Bi58 solder alloys, and also of copper (for a first orientation) and fused silica, which is used for the indenter calibration. Moreover, the potential change of material properties at elevated temperatures is investigated for the materials mentioned. A hot stage add-on allows nanoindentation measurements up to +500°C in order to characterize the various materials in great detail. The melting points of the solder alloys are 199°C and 138°C for Sn91Zn9 and Sn42Bi58, respectively. The prohibition of the lead containing eutectic SnPb solder alloy requires research work in lead-free materials. This paper describes the setup and the analysis of temperature-dependent material tests and presents first results for Young's modulus, hardness, and yield stress, which are compared to literature, at least as far as possible. Furthermore this paper has the goal to verify the measurement setup and the subsequent data evaluation.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126732610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Thin die stacking by low temperature In/ Au IMC based bonding method 基于低温In/ Au IMC键合方法的薄模堆积

2009 11th Electronics Packaging Technology Conference Pub Date : 2009-12-01 DOI: 10.1109/EPTC.2009.5416503

Siong Chiew Ong, W. Choi, C. Premachandran, E. Liao, Ling Xie

{"title":"Thin die stacking by low temperature In/ Au IMC based bonding method","authors":"Siong Chiew Ong, W. Choi, C. Premachandran, E. Liao, Ling Xie","doi":"10.1109/EPTC.2009.5416503","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416503","url":null,"abstract":"Low temperature bonding technology is developed using In-alloy on Au at a low temperature below 200˚C forming robust intermetallics (IMC) joints with high re-melting temperature (>300˚C), so that after bonding the IMC joints can withstand the subsequent processes without any degradation. Using similarly solder system and methodology, chips to wafer (C2W) bonding method has been developed, as such chips are temporary bonded onto wafer before the final bonding. The chips are bonded onto the wafer by two sequential bonding condition; temporary followed by a final bonding, which is 200/90˚C (chip/wafer) for 20sec and 180/180˚C for 5mins. The IMC joints are evaluated in terms of microstructure and compositional observations by means of scanning electron microscope (SEM) and transmittance electron microscope (TEM). As a result, it was confirmed that the joint was completely occupied with the Au-In based IMC phases. These IMC joint showed a tensile strength of 120~330N (23.5~38.8MPa). Based on this study, the 3 stacked dice with 8×8 mm2 dies with ~1700 I/Os of 80um solder bumps were fabricated in a chip to wafer stacking method. It showed uniform bonding all over the die in each layer with relatively good tensile strength achieved. Furthermore, it also underwent 3 times reflow test at 260˚C. The IMC joint was examined after going through the reflows test and the bonded samples exhibited neither de-lamination nor any changes in the microstructure.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114580250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Effect of split power/ground planes using stitching capacitors on radiated emission 采用拼接电容分割电源/地平面对辐射发射的影响

2009 11th Electronics Packaging Technology Conference Pub Date : 2009-12-01 DOI: 10.1109/EPTC.2009.5416488

Jang-Hoon Lee, Pilsoo Lee, Tae-Heon Lee, Chang-Gyun Kim, Inchae Song, J. Wee

引用次数: 7

Cross-interaction effect in the Ni/Sn/Cu solder joints Ni/Sn/Cu焊点的相互作用效应

2009 11th Electronics Packaging Technology Conference Pub Date : 2009-12-01 DOI: 10.1109/EPTC.2009.5416529

H. Tseng, S. Wang, C. Y. Liu

引用次数: 1

Reliability evaluation of fatigue life for solder joints in chip components considering shape dispersion 考虑形状分散的片状元件焊点疲劳寿命可靠性评价

2009 11th Electronics Packaging Technology Conference Pub Date : 2009-12-01 DOI: 10.1109/EPTC.2009.5416426

Y. Nishimura, Qiang Yu, T. Maruoka

{"title":"Reliability evaluation of fatigue life for solder joints in chip components considering shape dispersion","authors":"Y. Nishimura, Qiang Yu, T. Maruoka","doi":"10.1109/EPTC.2009.5416426","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416426","url":null,"abstract":"This paper presents mining the worst thermal fatigue life of solder joints on chip components used in vehicle electronics. The authors proposed an isothermal fatigue test method using real size solder joints to get the fatigue properties. The Manson-Coffin's law given by this method could improve the agreement between the simulation model and experimental results. Based upon the Manson-Coffin's law and Miner's law, the authors proposed a fatigue crack propagation simulation approach. By using this approach, the fatigue life of typical 36 cases with various solder shapes were examined. Thermal fatigue life to not only crack initiation but also crack propagation was evaluated by using the finite element method. When the crack propagates into a fillet of solder, the fatigue life drops to a lower value. Since there is an interaction between two solder joints on the chip component, asymmetrical structure also affects the fatigue life. It means that the shape of solder joints should be designed to control the failure mode. Considering scatter at 6σ level, such kind of the worst cases will exist and should be considered in design stage.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"193 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115633328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Interface reaction of Pb-free Sn-3.5Ag solder with Ni-Sn-P metallization 无铅Sn-3.5Ag钎料与Ni-Sn-P金属化的界面反应

2009 11th Electronics Packaging Technology Conference Pub Date : 2009-12-01 DOI: 10.1109/EPTC.2009.5416457

Y. Yang, P. Teh, A. Sumboja, Z. Chen

引用次数: 1

Development of high speed board level bend tester for drop impact applications 用于跌落冲击的高速板级弯曲试验机的研制

2009 11th Electronics Packaging Technology Conference Pub Date : 2009-12-01 DOI: 10.1109/EPTC.2009.5416542

S. M. Lim, Zhong Chen, H. Ng, T. Y. Tee, C. P. Khoo, Vincent Chng, F. L. Liu, K. T. Tsai

{"title":"Development of high speed board level bend tester for drop impact applications","authors":"S. M. Lim, Zhong Chen, H. Ng, T. Y. Tee, C. P. Khoo, Vincent Chng, F. L. Liu, K. T. Tsai","doi":"10.1109/EPTC.2009.5416542","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416542","url":null,"abstract":"Due to the widespread use of portable electronics, there is a significant increase in interest in exploring the impact reliability of electronic packaging during impact shock. Currently, the test standard used for board level drop testing is JESD 22-B111 [1], which specifies the impact pulse (i.e. 1500G at 0.5ms) as a criterion for drop testing. However, this may not mimic the actual product testing. The board level cyclic bend test standard (JESD 22-B113) [2] is subsequently developed and introduced to perform low frequency bending (1 to 3 Hz). However, cyclic bend at low frequency is not able to produce similar failure mode as drop testing because board frequency during drop impact is usually much higher. Thus in this study, a high speed bend test (>50Hz) is developed to perform strain-controlled bend testing. The strain amplitude and frequency effects on BGA and WLCSP package solder joint life on various board sizes and component layout are studied and discussed. An increase in frequency was found to result in a significant reduction in time to failure, though a shift in failure mode (from bulk solder to inter-metallic failure) and reduction in cycles to failure were not observed. Results indicated that at higher strain amplitudes, cycles to fatigue life of package significantly decreased. This study has also shown a certain extent of correlation between drop test and high speed bend test.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"197 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122988287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Effect of electromagnetic band-gap depredation by plating through hold in packaging application 在包装应用中电镀经把持对电磁带隙的侵蚀作用

2009 11th Electronics Packaging Technology Conference Pub Date : 2009-12-01 DOI: 10.1109/EPTC.2009.5416462

Y. Chuang, S. Wu

引用次数: 0

Electromagnetic interference suppression and simultaneous switching noise mitigation in system on package using a lowpass filter structure with embedded capacitor 采用嵌入电容的低通滤波器结构抑制系统的电磁干扰和同时抑制开关噪声

2009 11th Electronics Packaging Technology Conference Pub Date : 2009-12-01 DOI: 10.1109/EPTC.2009.5416460

Lei Li, Yunfeng Wang, L. Wan, Xiaoli Liu, Rongrong Sun, Shuhui Yu

{"title":"Electromagnetic interference suppression and simultaneous switching noise mitigation in system on package using a lowpass filter structure with embedded capacitor","authors":"Lei Li, Yunfeng Wang, L. Wan, Xiaoli Liu, Rongrong Sun, Shuhui Yu","doi":"10.1109/EPTC.2009.5416460","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416460","url":null,"abstract":"System on package (SOP) is an emerging technology, and provides an implementation options for system with small size, especially for mixed-signal systems. However, in such a compact package, noise generated by the digital chip can be easily coupled to the RF IC, and degrade the sensitivity of RF signal. In this paper, a simple and efficient multi-order lowpass filter for EMI and SSN suppression in system on package is implemented with embedded capacitor material. It has good performance in noise isolation with a small size of 10mm×mm. The lowpass filter is designed and simulated by electromagnetic analysis software, HFSS. The insertion loss is below −70dB from1.5GHz to 10GHz. Then, the lowpass filter is serial with a surface mounted 47nH inductor, and can achieve noise suppression below-50dB from 50MHz to 10GHz, below −60dB from 140MHz to 10GHz, and below −80dB from 600MHz to 10GHz. That is very promising for system on package application in mixed-signal systems. The structure can also be used in large scale backplanes or motherboards.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126127938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Bonding head design for thin wafer 薄晶圆焊头设计

2009 11th Electronics Packaging Technology Conference Pub Date : 2009-12-01 DOI: 10.1109/EPTC.2009.5416546

Chan-Hong Lee, Jaehak Lee, T. Ha, J. Song

引用次数: 1