2009 11th Electronics Packaging Technology Conference最新文献

{"title":"Assembly challenges for low modulus die attach material for MEMS devices","authors":"C. Lo, Ong Kar Yoke, C. Yong, L. Seong","doi":"10.1109/EPTC.2009.5416446","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416446","url":null,"abstract":"Packaging technique for MEMS devices such as selection of appropriate materials, proper process steps and approaches are crucial to meet the end product requirement in terms of overall package functionality and performances. Packaging MEMS devices requires low modulus die attach material due to their delicate intrinsic properties against interfacial mismatch as a result of thermo-mechanical stresses. Silicone based adhesives are good candidates as they exhibit properties of low modulus, 100 to 1000 times lower than conventional silica filled die attach epoxy. Manufacturability of such low modulus material often pose challenges at die attach in terms of bond line thickness, die attach material coverage, fillet height and planarity control. This paper discusses the impact of silicone based adhesive on wire bond ability. Material characterization through the use of thermo-gravimetric analyzer (TGA) and differential scanning calorimeter (DSC) to understand the adhesive curability and weight loss will also be discussed. Process robustness study through comprehensive DOE and optimization is important to meet the desired process capability index, Cpk. In addition, this paper will also explain the importance of staging duration from commence of die attach to curing process to assure the second wire bond strength is capable of meeting reliability requirement. The approaches used in this study are some of the challenges faced in producing a robust die attach material capable of meeting the various MEMS devices performance requirement.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126019047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Molecular dynamics study of the chiral vector influence on thermal conductivity of carbon nanotubes","authors":"T. Falat, B. Platek, J. Felba","doi":"10.1109/EPTC.2009.5416473","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416473","url":null,"abstract":"Current paper focuses on the influence of chiral vector on thermal conductivity of carbon nanotubes. The non-equilibrium molecular dynamic technique was implemented in commercially available software. The eleven single-walled CNTs of various chirality (from zigzag to armchair) was investigated. Moreover, the influence of length on CNTs thermal conductivity was examined.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122014671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thin wafer handling and processing-results achieved and upcoming tasks in the field of 3D and TSV","authors":"P. Kettner, J. Burggraf, Bioh Kim","doi":"10.1109/EPTC.2009.5416442","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416442","url":null,"abstract":"As microelectronic applications and technologies are getting more demanding, it is being demonstrated that the 3rd (vertical) dimension on wafer-processing technology is enabling applications and products with higher performance. Approaching the 3rd dimension in wafers is actually considered and realized through emerging TSV (through silicon via) technology and thinned wafers at the same time. Thin (<100 ¿m) silicon wafers which are commonly used for TSV formation exhibit increased instability and fragility. The lack of mechanical stability and the increased fragility present a major challenge to maintain high yield levels in volume manufacturing environments. The most accepted handling solution for UltraThin® wafers is the use of temporary bonding and debonding techniques utilizing a rigid carrier wafer to provide sufficient mechanical support. Once the product wafer is temporarily bonded to the carrier wafer, it is ready for backside processing including back-thinning, through-silicon via (TSV) formation, etc. The product wafers can be pre-processed wafers with CMOS devices as well as e.g. substrates with high-topographies like solder-balls. Additional stacking of ultra thin wafers or bonding chips to thin wafers are new requirements to be considered.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130272070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"X-ray computed tomography on miniaturized solder joints for nano packaging","authors":"M. Oppermann, T. Zerna, Klaus-Jurgen Wolter","doi":"10.1109/EPTC.2009.5416570","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416570","url":null,"abstract":"The challenge of nano packaging requires new nondestructive evaluation (NDE) techniques to detect and characterize very small defects like transportation phenomenon, Kirkendall voids or micro cracks. Imaging technologies with resolutions in the sub-micron range are the desire. But what does nano packaging mean? High end semiconductor industries today deal with functional structures down to 45 nm and below. ITRS roadmap predicts an ongoing decrease of the ?DRAM half pitch? over the next decade. Nano packaging of course is not intended to realize pitches at the nanometer scale, but has to face the challenges of integrating such semiconductor devices with smallest pitch and high pin counts into systems. System integration (SiP, SoP, Hetero System Integration etc.) into the third dimension is the only way to reduce the gap between semiconductor level and packaging level interconnection. The task is not only to identify any impurities on the package surface, but also to look as deep as possible into the package volume. Available non-destructive evaluation (NDE) methods for such kind of packaging are for example X-ray microscopy, X-ray computed tomography, ultrasonic microscopy and thermal microscopy. An overview was presented in. To investigate and discuss the limitations of the current NDE techniques and to find new ways to solve these problems the German government (Federal Ministry of Education and Research - BMBF) supports the research project ?Destructive and non-destructive evaluation techniques to characterize nano-scaled defects in highly miniaturized solder joints -nanoPAL?. The Electronics Packaging Lab and the Center of Microtechnical Manufacturing are the responsible institutions for the non-destructive testing part in this public project and main parts of the content of our presentation are results of this work focused on X-ray nano focus microscopy and nano focus computed tomography. This paper discusses the potentials and the limits of X-ray NDE techniques, illustrated by crack observation in solder joints, evaluation of micro vias in PCBs and interposers and the investigation of soldering quality of BGAs. The paper presents tomography results with voxel sizes (voxel: smallest gray scale unit / pixel with third dimension (cube)) less than 900nm and gives some information about the practical use of a computed tomography system.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130291978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A study on the thermal deformation and the mechanical properties due to curing process of the encapsulation resin","authors":"Hiroyuki Sato, Qiang Yu","doi":"10.1109/EPTC.2009.5416399","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416399","url":null,"abstract":"Since the flexural rigidity of thin semiconductor package become much lower than normal components, the warpage of the component become a much more important issue to evaluate the reliability. (1)In this study the author's proposal a new practical shrinkage method to measure the real time curing deformation and the elastic modulus resin during the whole curing process. the thermal deformation of the resin under curing was measured by using the optical digital image correlation method. Next, to examine the mechanical properties of the resin, the liquid resin was poured into an aluminum frame with thin sole, and the bending rigid of the aluminum frame was measured by the three points bending test every minutes at the curing temperature of the resin. Based upon the experimented result, the effect of curing shrinkage on the warpage of a CSP package was confirmed, and it was found that the shrinkage properties can affect not only the warpage of the component about also the thermal cyclic fatigue life.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130406107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Microchannel water cooling for LTCC based microsystems","authors":"Yangfei Zhang, Jia-Qi Chen, S. Bai, Yu-feng Jin, M. Miao, Jing Zhang","doi":"10.1109/EPTC.2009.5416475","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416475","url":null,"abstract":"The heat dissipation of six different types of microchannel networks integrated in LTCC based microsystems has been investigated by experimental measurement and simulation analysis, including straight, serpentine, spiral and fractal-shaped microchannel networks of curve, I-shaped and parallel. The cross section of microchannel is 200 μm × 200 μm and the total length is about 200 mm. The water mass flow rate at the inlet was controlled at 7.5 ml/min by a powerful micro-bump and the heat flux of surface heating area was supplied from 0.2 W/cm2 to 1 W/cm2 by an array of chip resistors. The simulated maximum temperature rise by finite volume method agrees well with the experimental results. It is found that the spiral microchannel has the best cooling ability and reduces 86.8% of the maximum temperature rise at 1 W/cm2. The microchannels are proved to have little effect on the strength of the substrate by finite element analysis method due to the small size of cross section.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127311274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Polymer filling of medium density through silicon via for 3D-packaging","authors":"P. Chausse, M. Bouchoucha, D. Henry, N. Sillon, L. Chapelon","doi":"10.1109/EPTC.2009.5416443","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416443","url":null,"abstract":"In this paper, we present some process developments and polymer material evaluations done to achieve the complete filling of 3D-WLP via. The test wafers used for these studies were either blankets with several via sizes specifically designed to determine via filling process window, or wafers with patterns and stacking which result from a real set-top box demonstrator. Initially, the 3D-WLP integration scheme of the demonstrator which required complete via filling is presented. Then the different test structures and patterns needed to characterize via filling behavior are described. Two methods for via filling are exposed and discussed: spin-on process of liquid polymers and vacuum assisted lamination of dry film resists. Some results concerning filling morphology with dedicated polymers are presented for both methods. After that, the defined set of chemical, mechanical and electrical properties chosen to select the polymers is given and explained. Finally, some materials which fulfill previously defined requirements are evaluated and characterized.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128873346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Crack and damage evaluation in low-k BEoL structures under CPI aspects","authors":"J. Auersperg, D. Vogel, M. Lehr, M. Grillberger, B. Michel","doi":"10.1109/EPTC.2009.5416478","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416478","url":null,"abstract":"Miniaturization and increasing functional integration as the electronic industry drives force the development of feature sizes down to the nanometer range. Moreover, harsh environmental conditions and new porous or nano-particle filled materials introduced on both chip and package level - low-k and ultra low-k materials in Back-end of line (BEoL) layers of advanced CMOS technologies, in particular — cause new challenges for reliability analysis and prediction. The authors show a combined numerical/experimental approach and results towards optimized fracture and fatigue resistance of those structures under chip package interaction (CPI) aspects by making use of bulk and interface fracture concepts, VCCT, X-FEM and cohesive zone models in multi-scale and multi-failure modeling approaches with several kinds of failure/fatigue phenomena. Probable crack paths and interactions between material damaging, ratcheting and interface fracture will be discussed. Complementary to the simulation side of reliability estimations, serious issues are connected with the collection of appropriate material properties in the miniaturized range addressed — Young's modulus, initial yield stress, hardening. Nano-indentation, AFM, FIB and EBSD provide these desired properties, in particular. In addition, residual stresses in the back-end layer stack caused by the different manufacturing processes have an essential impact on damage behavior, because they superpose functional and environmental loads. Their determination with a spatial resolution necessarily for typical BEoL structure sizes is shown with the help of a nano-scale stress relief technique (FIBDAC) that makes use of tiny trenches placed with a focused ion beam (FIB) equipment and digital image correlation algorithms.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128889864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Improving reliability of lateral thermosonic flip-chip bonding with ACF","authors":"Chang-Wan Ha, Kyung-Soo Kim","doi":"10.1109/EPTC.2009.5416577","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416577","url":null,"abstract":"For interconnection of liquid crystal display (LCD) driver IC, in this paper, thermosonic (TS) flip chip bonding technique which utilizes a lateral ultrasonic vibration as an additional heat source is considered. Larger amplitude of vibration produces more heat energy, which would accelerate the curing process of epoxy. In order to avoid potential problems due to large vibration amplitude such as misalignment between bump and pad, and the plastic deformation of epoxy resin, the viscoelastic characteristics of ACF epoxy are investigated. Based on experimental results, a useful guideline to determine the vibration amplitude is newly proposed. Moreover, the experimental results clearly show the relationship between curing degree and reliable amplitude range of vibration.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130138582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Challenges for extra large embedded wafer level ball grid array development","authors":"J. Luan, Yonggang Jin, K. Goh, Yiyi Ma, G. Hu, Yaohuang Huang, X. Baraton","doi":"10.1109/EPTC.2009.5416551","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416551","url":null,"abstract":"Fan-out embedded wafer level ball grid array (eWLB) is a very promising packaging technology with many advantages in comparison to standard Ball Grid Array Packages and leadframe based packages because of smaller size, better electrical and thermal performance, higher package interconnect density and system integration possibilities at low packaging cost. It was successfully developed for medium and large-size package. However, there is strong need to develop extra large eWLB for system integration. Compared with large eWLB, there are many challenges for extra large eWLB development. Wafer or panel level warpage, package level reliability, and board level reliability are ones of the most challenging issues. In this paper, finite element modeling was used to create design rules and optimize test vehicles based on the correlation done for medium, large-size eWLB. Two test vehicles were indentified for process development and reliability test. Recent progress in the extra large eWLB development is introduced in this paper, the results show that the design rule and process capability are reliable and ready for extra large molded embedded wafer level package for system integration needs.","PeriodicalId":256843,"journal":{"name":"2009 11th Electronics Packaging Technology Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129873185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}