Crack and damage evaluation in low-k BEoL structures under CPI aspects

Miniaturization and increasing functional integration as the electronic industry drives force the development of feature sizes down to the nanometer range. Moreover, harsh environmental conditions and new porous or nano-particle filled materials introduced on both chip and package level - low-k and ultra low-k materials in Back-end of line (BEoL) layers of advanced CMOS technologies, in particular — cause new challenges for reliability analysis and prediction. The authors show a combined numerical/experimental approach and results towards optimized fracture and fatigue resistance of those structures under chip package interaction (CPI) aspects by making use of bulk and interface fracture concepts, VCCT, X-FEM and cohesive zone models in multi-scale and multi-failure modeling approaches with several kinds of failure/fatigue phenomena. Probable crack paths and interactions between material damaging, ratcheting and interface fracture will be discussed. Complementary to the simulation side of reliability estimations, serious issues are connected with the collection of appropriate material properties in the miniaturized range addressed — Young's modulus, initial yield stress, hardening. Nano-indentation, AFM, FIB and EBSD provide these desired properties, in particular. In addition, residual stresses in the back-end layer stack caused by the different manufacturing processes have an essential impact on damage behavior, because they superpose functional and environmental loads. Their determination with a spatial resolution necessarily for typical BEoL structure sizes is shown with the help of a nano-scale stress relief technique (FIBDAC) that makes use of tiny trenches placed with a focused ion beam (FIB) equipment and digital image correlation algorithms.