[1993 Proceedings] Fifth Biennial Nonvolatile Memory Technology Review最新文献

{"title":"A Viable NDRO FERRAM Dielectric Structure","authors":"D. Lampe, I.W. Dzimianski, D. Adams, H. Buhay, S. Sinharoy, M.H. Francombe","doi":"10.1109/NVMT.1993.696947","DOIUrl":"https://doi.org/10.1109/NVMT.1993.696947","url":null,"abstract":"Research efforts at Westinghouse over the past three years have demonstrated the use of multi-layered gate dielectric structures in integrated ferroelectric memory field-effect transistors (FEMFETs). Such gate structures include both ferroelectric films and high-quality non-ferroelectric insulating buffer-andcapping layers. These layers, which usually comprise SiO, and Si,N,, perform vital functions by (a) suppressing tunneling/ trapping of charge from the silicon into the ferroelectric film, (b) inhibiting chemical interaction at the interface with the ferroelectric layer, (c) enhancing the breakdown strength and electrical stabilty of the gate structure, and (d) passivating the gate dielectric against subsequent high-temperature processing.","PeriodicalId":254731,"journal":{"name":"[1993 Proceedings] Fifth Biennial Nonvolatile Memory Technology Review","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125085136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"On The Total Dose Radiation Hardness Of Floating Gate EEPROM Cells","authors":"D. Wellekens, G. Groeseneken, J. van Houdt, H. Maes","doi":"10.1109/NVMT.1993.696956","DOIUrl":"https://doi.org/10.1109/NVMT.1993.696956","url":null,"abstract":"In this paper the total dose radiation response of single and double polysilicon floating gate EEPROM cells is compared. While the hardness of double polysilicon cells is restricted to a few kilorads, devices having only one polysilicon layer are shown to be much more radiation-hard. A model is presented, that is able to explain the different behaviour of both types of cells and guidelines are given to improve the radiation hardness of the cells.","PeriodicalId":254731,"journal":{"name":"[1993 Proceedings] Fifth Biennial Nonvolatile Memory Technology Review","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134111612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Error Detection And Management Approach For Nonvolatile Electrically Erasable And Programmable Read Only Memory (EEPROM) Systems","authors":"H.F. Hoffman, M. Sebas, R. Desimone, P. Ebersold, J. Smeltzer","doi":"10.1109/NVMT.1993.696965","DOIUrl":"https://doi.org/10.1109/NVMT.1993.696965","url":null,"abstract":"This paper describes an approach for detecting and managing bit failures in bulk storage memory systems. This error management scheme is particularly suitable for electrically erasable and programmable Read Only Memory (EEPROM) devices used in applications requiring repetitive write operations. Norden Systems' Need Norden Systems manufactures a Fire Control System (FCS) for the US Army's Multiple Launch Rocket System (MLRS). One of the line replaceable unit (LRU) comprising the FCS contains a Bulk Storage Memory Unit (BSMU) for non-volatile repetitive data storage that uses bubble memory devices. The sole source manufacturer, Hitachi, intends to discontinue bubble memory device manufacturing in the near future. Hitachi offered the user a final opportunity to purchase components. This option is costly and does not ensure an adequate supply of parts for present spares support or future build requirements. Since the present MLRS FCS is to remain in production for the next five years and continue to be fielded for the next ten years, Norden undertook an effort to find an inexpensive, reliable replacement technology for the obsolescent bubble memory device. The new Circuit Card Assembly (CCA) was intended to be a form, fit and function replacement for the existing BSMU. The replacement CCA had to communicate with the host unit's backplane bus and retain the existing BSMU connector pin assignments.","PeriodicalId":254731,"journal":{"name":"[1993 Proceedings] Fifth Biennial Nonvolatile Memory Technology Review","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130215363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The Impact Of Japanese Producers On Flash Memories","authors":"H. L. Mette","doi":"10.1109/NVMT.1993.696952","DOIUrl":"https://doi.org/10.1109/NVMT.1993.696952","url":null,"abstract":"Although Intel still holds 85% of the global flash memory market and is now offering 8Mb devices, NEC, Hitachi, Fujitsu and Matsushita have each developed basic technologies to create the next generation of 16Mb and higher flash devices. These companies are expected to acquire an increasing share of the overall flash memory market, which according to some estimates will increase from $130 million in 1992 to $1.5 billion in 1995 worldwide.","PeriodicalId":254731,"journal":{"name":"[1993 Proceedings] Fifth Biennial Nonvolatile Memory Technology Review","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123775597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Automated SONOS NVSM Dynamic Characterization System","authors":"A. Banerjee, Yin Hu, M.G. Martin, M. White","doi":"10.1109/NVMT.1993.696957","DOIUrl":"https://doi.org/10.1109/NVMT.1993.696957","url":null,"abstract":"AbsiraeC A completely automated test station for performing exhaustive measurements on nonvolatile semiconductor memories has been designed and implemented. This is very cost effective as it uses in-house built instrumentation. Time-controlled pulses are applied to the device under test making it undergo the different modes of memory operation. Software has been developed to perform series of measurements to generate erase/write, retention and endurance curves of SONOS transistors. The entire apparatus may be controlled by any computer with an IEEE488 bus access. This setup has been used to study the reliability of SONOS devices.","PeriodicalId":254731,"journal":{"name":"[1993 Proceedings] Fifth Biennial Nonvolatile Memory Technology Review","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123871916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 1.6 Volt Operating Serial EEPROM","authors":"S. Awsare, Lan Lee, K. Su, A. Lin, S. Yeh","doi":"10.1109/NVMT.1993.696960","DOIUrl":"https://doi.org/10.1109/NVMT.1993.696960","url":null,"abstract":"A 1.6 Volt Operating Serial EEPROM Saleel Awsare, Lan Lee, Ken Su, Alan Lin and Sam Yeh Exel Microelectronics, A Division of Rohm Corporation, San Jose, CA A new CMOS 1K EEPROM memory with wide operating voltage range is described herein. This device can perform write or erase operations from 1.6V to 6V and read operations from 1.4V to 6V. Furthermore, the standby current is 0.5uA over the complete operating voltage range. Additionally, the active current is limited to 500uA at Vcc=6V. Design and processing techniques are optimized to achieve the low voltage and low current operation. I\" Advances in nonvolatile memories makes it possible to use EEPROM devices in portable applications. An EEPROM is an ideal nonvolatile memory device, since it is in-system reprogrammable using a single power supply. Some of the portable applications are cameras, cordless phones, stereo headphones, remote controls and pagers. These products require low voltage operation and very low current consumption in standby mode. Additionally, the products use two 1.2 V batteries thus requiring a minimum operating range from 1.8 V to 2.4 V. Therefore the demand for EEPROM's to operate at this range. This paper describes a CMOS 1K bit serial EEPROM, organized as 64 registers of 16 bits each. Seven 1 1 -bit instructions control the operation of the device, which includes read, write and mode enable operations. Each mode begins with a Start Bit, followed by the opcode, the address field, and data if appropriate. CIRCUIT TECHNOLOGY An EEPROM which functions at a wide voltage range requires changes from traditional design techniques. The areas of design addressed were the voltage multiplier, ring oscillator, Vpp ramp control circuit, write time control circuit, high voltage switch, and sense amplifier. The programming voltage (Vpp) required for erasing and programming the cell is 16V. This volta e is generated by using a voltage multiplier circuit [' I. The 0-7803-1290-2/93 53.00 01993 IEEE 92 1993 NONVOLATILE MEMORY TECHNOLOGY REVIEW voltage multiplier circuit has 20 stages. Each stage consists of an inter-plysilicon capacitor and a native device used as a diode. The native devices are used to give maximum voltage at lower power supply voltages. The first diode of the voltage multiplier circuit is a lightly doped enhancement (EMOS) device to prevent leakage. The oscillator which drives the voltage multiplier circuit is designed with a negative voltage coefficient to provide improved programming and emse voltage at lower power supply voltage. Figure 1 shows the voltage vs. frequency of the oscillator. Constant Vpp ramp time is achieved by using a very constant current source over voltage and temperature, thus maintaining a constant ramp time over the wide voltage range. Constant write (twp) time is achieved by using a oscillator which generates a constant frequency over the voltage range. The frequency is then divided to get the appropriate write time. The sense amplifier was desig","PeriodicalId":254731,"journal":{"name":"[1993 Proceedings] Fifth Biennial Nonvolatile Memory Technology Review","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131336475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 5v/3.3v-compatible Flash E/sup 2/PROM Cell With A 400ns/70/spl mu/m Programming Time For Embedded Memory Applications","authors":"J. van Houdt, D. Wellekens, L. Haspeslagh, L. Deferm, G. Groeseneken, H. Maes","doi":"10.1109/NVMT.1993.696951","DOIUrl":"https://doi.org/10.1109/NVMT.1993.696951","url":null,"abstract":"","PeriodicalId":254731,"journal":{"name":"[1993 Proceedings] Fifth Biennial Nonvolatile Memory Technology Review","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133415513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Labelling With Silicon One-conductor, Nonvolatile Memory Technology For Attaching Digital Data To Objects","authors":"M. Bolan","doi":"10.1109/NVMT.1993.696939","DOIUrl":"https://doi.org/10.1109/NVMT.1993.696939","url":null,"abstract":"The concept of labelling is simple. Information accompanies an object to supply on-the-spot data to whomever needs it. Computer-readable labels offer even greater value because of the speed and accuracy with which information can be read. However, the need to keep information current on the labels in a dynarmc process begs for a more powerful medium than paper labels, which must be removed, re-printed, and replaced in order to be updated. Just as word processing has revolutionized the writing process by facilitating editing and subsequent communication, silicon will change the role of labels in the design of a modem data collection system. Chip-based labels become instant sources of digital information for the objects they escort.","PeriodicalId":254731,"journal":{"name":"[1993 Proceedings] Fifth Biennial Nonvolatile Memory Technology Review","volume":"228 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114000812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"One Megabit Memory Chip Using Giant Magnetoresistive Memory Cells","authors":"J.L. Brown, A.V. Pohm, S.A. Mundon, R. Sinclair, D.K. Cooper, W. Black, T. Dupuis, J. Daughton","doi":"10.1109/NVMT.1993.696950","DOIUrl":"https://doi.org/10.1109/NVMT.1993.696950","url":null,"abstract":"J. L. Brown, A. V. Pohm, S. A. Mundon, R. A. Sinclair, D. K. Cooper, W. C. Black, T. J. Dupuis, J. M. Daughton Nonvolatile Electronics Inc., 12800 Industrial Park Blvd., Plymouth, MN 5544","PeriodicalId":254731,"journal":{"name":"[1993 Proceedings] Fifth Biennial Nonvolatile Memory Technology Review","volume":"144 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121639385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Temperature Transients In Normal And Giant Magneto-resistance Memory Cells","authors":"A.V. Pohm, C. Comstock, C. Kohl, I. Ranrnuthu, K. Ranmuthu","doi":"10.1109/NVMT.1993.696936","DOIUrl":"https://doi.org/10.1109/NVMT.1993.696936","url":null,"abstract":"Current developmental magneto-resist ive memories using normal material (AMR, anisotropic magneto-resistance) operate with current densities of about 6 million Amps per square centimeter in the magneto-resistive double layers(1). The double layers have a sheet resistance of 10 ohms per square and are deposited onto a half micron thick silicon dioxide layer coveriny the gate poly silicon in the CMOS integrated circuitry used. In this environment, significant heating of the memory elements takes place with most of the temperature rise occurring within a microsecond. If the memory arrays are not properly designed, the increase in resistance arising from heating can obscure the resistance change generated by application of the word field during the read operation. In the case of memory elements made with the developmental giant magneto-resist ive (GMR) material, the temperature rise for the same dielectric thickness is larger because the sheet resistances are typically in the 15 to 25 ohms per square range. Because thermal effects are an important design consideration, analytical and experimental studies were undertaken to examine the thermal behavior of normal and giant magneto-resistive memory cell structures.","PeriodicalId":254731,"journal":{"name":"[1993 Proceedings] Fifth Biennial Nonvolatile Memory Technology Review","volume":"519 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116262239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}