D. Lampe, I.W. Dzimianski, D. Adams, H. Buhay, S. Sinharoy, M.H. Francombe
{"title":"A Viable NDRO FERRAM Dielectric Structure","authors":"D. Lampe, I.W. Dzimianski, D. Adams, H. Buhay, S. Sinharoy, M.H. Francombe","doi":"10.1109/NVMT.1993.696947","DOIUrl":null,"url":null,"abstract":"Research efforts at Westinghouse over the past three years have demonstrated the use of multi-layered gate dielectric structures in integrated ferroelectric memory field-effect transistors (FEMFETs). Such gate structures include both ferroelectric films and high-quality non-ferroelectric insulating buffer-andcapping layers. These layers, which usually comprise SiO, and Si,N,, perform vital functions by (a) suppressing tunneling/ trapping of charge from the silicon into the ferroelectric film, (b) inhibiting chemical interaction at the interface with the ferroelectric layer, (c) enhancing the breakdown strength and electrical stabilty of the gate structure, and (d) passivating the gate dielectric against subsequent high-temperature processing.","PeriodicalId":254731,"journal":{"name":"[1993 Proceedings] Fifth Biennial Nonvolatile Memory Technology Review","volume":"55 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1993 Proceedings] Fifth Biennial Nonvolatile Memory Technology Review","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NVMT.1993.696947","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Research efforts at Westinghouse over the past three years have demonstrated the use of multi-layered gate dielectric structures in integrated ferroelectric memory field-effect transistors (FEMFETs). Such gate structures include both ferroelectric films and high-quality non-ferroelectric insulating buffer-andcapping layers. These layers, which usually comprise SiO, and Si,N,, perform vital functions by (a) suppressing tunneling/ trapping of charge from the silicon into the ferroelectric film, (b) inhibiting chemical interaction at the interface with the ferroelectric layer, (c) enhancing the breakdown strength and electrical stabilty of the gate structure, and (d) passivating the gate dielectric against subsequent high-temperature processing.