A 1.6 Volt Operating Serial EEPROM

Abstract

A 1.6 Volt Operating Serial EEPROM Saleel Awsare, Lan Lee, Ken Su, Alan Lin and Sam Yeh Exel Microelectronics, A Division of Rohm Corporation, San Jose, CA A new CMOS 1K EEPROM memory with wide operating voltage range is described herein. This device can perform write or erase operations from 1.6V to 6V and read operations from 1.4V to 6V. Furthermore, the standby current is 0.5uA over the complete operating voltage range. Additionally, the active current is limited to 500uA at Vcc=6V. Design and processing techniques are optimized to achieve the low voltage and low current operation. I" Advances in nonvolatile memories makes it possible to use EEPROM devices in portable applications. An EEPROM is an ideal nonvolatile memory device, since it is in-system reprogrammable using a single power supply. Some of the portable applications are cameras, cordless phones, stereo headphones, remote controls and pagers. These products require low voltage operation and very low current consumption in standby mode. Additionally, the products use two 1.2 V batteries thus requiring a minimum operating range from 1.8 V to 2.4 V. Therefore the demand for EEPROM's to operate at this range. This paper describes a CMOS 1K bit serial EEPROM, organized as 64 registers of 16 bits each. Seven 1 1 -bit instructions control the operation of the device, which includes read, write and mode enable operations. Each mode begins with a Start Bit, followed by the opcode, the address field, and data if appropriate. CIRCUIT TECHNOLOGY An EEPROM which functions at a wide voltage range requires changes from traditional design techniques. The areas of design addressed were the voltage multiplier, ring oscillator, Vpp ramp control circuit, write time control circuit, high voltage switch, and sense amplifier. The programming voltage (Vpp) required for erasing and programming the cell is 16V. This volta e is generated by using a voltage multiplier circuit [' I. The 0-7803-1290-2/93 53.00 01993 IEEE 92 1993 NONVOLATILE MEMORY TECHNOLOGY REVIEW voltage multiplier circuit has 20 stages. Each stage consists of an inter-plysilicon capacitor and a native device used as a diode. The native devices are used to give maximum voltage at lower power supply voltages. The first diode of the voltage multiplier circuit is a lightly doped enhancement (EMOS) device to prevent leakage. The oscillator which drives the voltage multiplier circuit is designed with a negative voltage coefficient to provide improved programming and emse voltage at lower power supply voltage. Figure 1 shows the voltage vs. frequency of the oscillator. Constant Vpp ramp time is achieved by using a very constant current source over voltage and temperature, thus maintaining a constant ramp time over the wide voltage range. Constant write (twp) time is achieved by using a oscillator which generates a constant frequency over the voltage range. The frequency is then divided to get the appropriate write time. The sense amplifier was designed to guarantee a wide voltage operation. This circuit senses the current flow through the EEPROM cell. A PMOS transistor was used to pull the data line to above the trip-point of the sense amplifier to read an erased cell, causing the output of the sense amplifier to be a high. To read a programmed cell, the cell current overrides the PMOS pull-up device, pulling the data line below the trip-point of the sense amplifier outputting a low. To maximize the current flow in the read path and minimize the threshold voltage drop into the array, EMOS devices are used for bit line select and sense line select devices. A high voltage switch circuit was designed to meet low voltage operation. This circuit switches Vpp voltage into the array and the decoding circuitry. To eliminate threshold drop into the array, a PMOS device is used to switch the full Vcc or full Vpp voltages. This circuit outputs three voltage levels, Ov for unselected word lines and bit lines, Vcc voltage for selected word-lines during read, Vpp voltage for the selected word-line during erase or program. Figure 2 shows the schematic of the high voltage switch. This low voltage product is processed in a n-well, double plysilicon, single metal technology. The periphery circuits use devices with 400 A gate oxide. This gate oxide is used for both high voltage and low voltage devices, and are processed with DDD features. Tunnel oxide is 90 A and the oxide equivalent of the inter-polysilicon dielectric (ONO) is 250 A. The key device features are presented in Table 1. TABLE 1. Key Features LL STRUCTU RE AND PE RFORMANCE Figure 3 shows the cross section of the low voltage EEPROM cell. Polysilicon 1 is used for the floating gate. Polysilicon 2 is used for the select gate and periphery transistors. The tunnel drain and source is formed prior to floating gate by tunnel implant and is 93 1993 NONVOLATILE MEMORY TECHNOLOGY REVIEW merged with source region of the select gate transistor during N+ source/drain formation. Cellsize vpp Vte 03 1 2 0 ~ 1 2 16V 5.75V Vtp I C ~ U (VI (UA) -1.6V 12uA