[1993 Proceedings] Fifth Biennial Nonvolatile Memory Technology Review最新文献

{"title":"MASIC Products Bring Adaptability To Embedded Systems","authors":"R. Kabidi, R. Orlando","doi":"10.1109/NVMT.1993.696941","DOIUrl":"https://doi.org/10.1109/NVMT.1993.696941","url":null,"abstract":"Introduction The embedded control market has been traditionally hampered by the inability to update operating parameters and fmware in a simple manner once the embedded system is installed in the field. While the standardization of the hard disk drive and load-and-execute memory hierarchy have simplified this process in the PC or workstation type of products, this approach is not suitable for the embedded systems due to the cost and complexity of the additional components required. E2PROM and Flash EPROM memories have been utilized in the past for this application, but their complex interface requirements and programming algorithms make them impractical in most embedded applications. The basic challenge in adding alterability through software modification is that the majority of the software in an embedded control system is stored in a semiconductor nonvolatile memory, such as a ROM, EPROM, Flash EPROM or E2PROM. Those devices which are alterable, share a common problem in that the process of updating the contents of the device is a programming sequence. As a result, the devices normally require a complex algorithm or extemal support hardware to accomplish the programming step. The Initial Program Load (IPL) is also a programming step, even for the most user friendly alterable nonvolatile memories, the E2PROMs. The SLICW (Self Loading Integrated Code) E2PROM product family solve these problems. The SLIC family concept is acombination of an byte alterable nonvolatile memory specifically designed to serve as a program and/or data memory for a particular microcontroller and embedded fmware routines written in the native code of the microcontroller. The purpose of the fmware routines is to download the applications software through the microcontroller’s Universal Asynchronous Receiver Transmitter WART) either at IPL or at any time one the system has been delivered to the end customer. The SLIC family of devices provide a simple method of updating or changing software in embedded control systems once the systems are in place in customers sites. The actual update mechanism could be through RS-232, modem or RF link.","PeriodicalId":254731,"journal":{"name":"[1993 Proceedings] Fifth Biennial Nonvolatile Memory Technology Review","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133056747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Contactless Reprogrammable Nonvolatile Memory Storage And Transmission","authors":"G. Miller, D. Sweetman","doi":"10.1109/NVMT.1993.696940","DOIUrl":"https://doi.org/10.1109/NVMT.1993.696940","url":null,"abstract":"A variety of applications require the use of a reprogrammable nonvolatile memory that can receive and transmit data without physical contact. Such applications include: debitlcredit cards, ticketdpasses, identification tags for cargo or personnel. These applications have in common the need to send and receive data without physical contact, to retain data without a power supply, and to alter the stored data in real time. Thin oxide floating gate EEPROMs fabricated on a 1.5 p BiCMOS process provide these functions. Two RF (radio frequency) coils are used to receive power and data from the transmitter and to send data to the receiver, i.e., up to 2 feet of separation. Single chip or two chip solutions are available, depending on the memory density required, e.g., up to 16K bits. EEPROM control fuses are used to optimize demodulation sensitivity and carrier frequency ranges. Data can be transferred at up to 19.2k baud using a serial format consisting of a start bit, 8 data bits, a parity bit, and a stop bit. This paper will describe the design techniques used to implement these features. Details will be provided for the operating specifications of such devices.","PeriodicalId":254731,"journal":{"name":"[1993 Proceedings] Fifth Biennial Nonvolatile Memory Technology Review","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115870130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Nonvolatile Memory Multi-chip Module","authors":"A. Gossard, J. Holland, E. Lawhou, D. Partridge","doi":"10.1109/NVMT.1993.696958","DOIUrl":"https://doi.org/10.1109/NVMT.1993.696958","url":null,"abstract":"A Nonvolatile Memory Multi-Chip Module (NVM MCM) has been developed that can be used as a building block for bulk nonvolatile memory boards or to provide nonvolatile memory for processor boards. The memory is organized as a 256Kilowords by 40-bits device. The device is packaged as a 1.45\" x 1.45\" ceramic leadless solder-free-interconnect padgrid-may. The NVM MCM supports the \"L-Bus\" protocol of the Intel 80960MC. This protocol defines a 32-bit multiplexed address and data bus and allows burst lransfers of up to four words. Module circuitry includes address decode, registered addresses, up to four-word burst read cycles, and program and erase capability. This MCM consists of five 256K x 8 twelvevolt Flash EPROMs, two Octal registers, two PALS and one Quad two-input NAND gate.","PeriodicalId":254731,"journal":{"name":"[1993 Proceedings] Fifth Biennial Nonvolatile Memory Technology Review","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127779966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Methods Of Achieving Nonvolatility In Solid State Disks","authors":"B. Kaufman","doi":"10.1109/NVMT.1993.696944","DOIUrl":"https://doi.org/10.1109/NVMT.1993.696944","url":null,"abstract":"Solid state disks are coming into wide use in a variety of applications, where they replace rotating disks to achieve dramatic improvements in speed and MTBF; especially in severe environments. While rotating disks are inherently nonvolatile, solid state disks implemented with DRAM or SRAM devices are inherently volatile. Retention of stored data under power-down conditions is commonly required and is often mission critical. To meet this requirement, a number of backup methods have been utilized to provide varying degrees of nonvolatility. These include: dumping to the host system, batteries, UPS, backup to disk and tape media, and hierarchal memory systems allowing loss of the stored data in the solid state disk. More recently, inherently nonvolatile semiconductor devices are being applied to eliminate backing stores or the need for energy","PeriodicalId":254731,"journal":{"name":"[1993 Proceedings] Fifth Biennial Nonvolatile Memory Technology Review","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117280821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}