{"title":"Nonvolatile Memory Multi-chip Module","authors":"A. Gossard, J. Holland, E. Lawhou, D. Partridge","doi":"10.1109/NVMT.1993.696958","DOIUrl":null,"url":null,"abstract":"A Nonvolatile Memory Multi-Chip Module (NVM MCM) has been developed that can be used as a building block for bulk nonvolatile memory boards or to provide nonvolatile memory for processor boards. The memory is organized as a 256Kilowords by 40-bits device. The device is packaged as a 1.45\" x 1.45\" ceramic leadless solder-free-interconnect padgrid-may. The NVM MCM supports the \"L-Bus\" protocol of the Intel 80960MC. This protocol defines a 32-bit multiplexed address and data bus and allows burst lransfers of up to four words. Module circuitry includes address decode, registered addresses, up to four-word burst read cycles, and program and erase capability. This MCM consists of five 256K x 8 twelvevolt Flash EPROMs, two Octal registers, two PALS and one Quad two-input NAND gate.","PeriodicalId":254731,"journal":{"name":"[1993 Proceedings] Fifth Biennial Nonvolatile Memory Technology Review","volume":"28 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1993 Proceedings] Fifth Biennial Nonvolatile Memory Technology Review","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NVMT.1993.696958","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A Nonvolatile Memory Multi-Chip Module (NVM MCM) has been developed that can be used as a building block for bulk nonvolatile memory boards or to provide nonvolatile memory for processor boards. The memory is organized as a 256Kilowords by 40-bits device. The device is packaged as a 1.45" x 1.45" ceramic leadless solder-free-interconnect padgrid-may. The NVM MCM supports the "L-Bus" protocol of the Intel 80960MC. This protocol defines a 32-bit multiplexed address and data bus and allows burst lransfers of up to four words. Module circuitry includes address decode, registered addresses, up to four-word burst read cycles, and program and erase capability. This MCM consists of five 256K x 8 twelvevolt Flash EPROMs, two Octal registers, two PALS and one Quad two-input NAND gate.