{"title":"Creation and evaluation of compact models for thermal characterisation using dedicated optimisation software","authors":"C. Lasance, D. den Hertog, P. Stehouwer","doi":"10.1109/STHERM.1999.762447","DOIUrl":"https://doi.org/10.1109/STHERM.1999.762447","url":null,"abstract":"The collaborative European project DELPHI, completed in November 1996, was concerned with the creation and experimental validation of thermal models for a range of electronic parts. Many DELPHI principles and results have been extensively discussed in open literature over the last five years (e.g. Rosten et al. 1997; Lasance et al. 1997); however, one of the topics that has not been treated in sufficient detail is the creation and evaluation or the compact models themselves. This paper tries to fill this gap. We have shown that a dedicated optimisation tool can have the potential to create models and to investigate the consequences of changing the model or the set of boundary conditions. It paves the way to thermal data-on-demand, a procedure by which a supplier provides the end-user with a model that is either suitable for all applications or tuned to a specific application, in almost real time.","PeriodicalId":253023,"journal":{"name":"Fifteenth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (Cat. No.99CH36306)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125399832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Composite Materials for Electronic Packaging and Thermal Management","authors":"C. Zweben","doi":"10.1109/STHERM.1999.762420","DOIUrl":"https://doi.org/10.1109/STHERM.1999.762420","url":null,"abstract":"This paper discusses the investigation of module cooling utilizing an enhanced thermosyphon heat loop as an alternative to direct air cooling or liquid-to-air cooling with forced convection of the liquid. Using water as the working fluid in the thermosyphon. experiments were conducted investigating the effects of fill volume, heat load, and condenser air flow rate on overall thermosyphon performance in terms of thermal resistance. Enhancement of evaporator performance using fins was also investigated and the results are reported in the paper.","PeriodicalId":253023,"journal":{"name":"Fifteenth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (Cat. No.99CH36306)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127310789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Teertstra, M. Yovanovich, J. Culham, T. Lemczyk
{"title":"Analytical forced convection modeling of plate fin heat sinks","authors":"P. Teertstra, M. Yovanovich, J. Culham, T. Lemczyk","doi":"10.1109/STHERM.1999.762426","DOIUrl":"https://doi.org/10.1109/STHERM.1999.762426","url":null,"abstract":"An analytical model is presented that predicts the average heat transfer rate for forced convection air cooled plate fin heat sinks for use in the design and selection of heat sinks for electronics applications. Using a composite solution based on the limiting cases of fully-developed and developing flow between isothermal parallel plates, the average Nusselt number can be calculated as a function of the heat sink geometry and fluid velocity. The resulting model is applicable for the full range of Reynolds number, 0.1<Re/sub b/*<100, and accurately predicts the experimental results to within an RMS difference of 2.1%.","PeriodicalId":253023,"journal":{"name":"Fifteenth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (Cat. No.99CH36306)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125612913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Junction-to-top and junction-to-board thermal resistance measurement for 119 BGA packages","authors":"T. Chung, M. Kim, J. Baek, S. Oh","doi":"10.1109/STHERM.1999.762441","DOIUrl":"https://doi.org/10.1109/STHERM.1999.762441","url":null,"abstract":"Junction-to-top (/spl theta//sub jt/) and junction-to-board (/spl theta//sub jb/) thermal resistance of a 119 BGA package for 4 Mbit SP SRAM have been investigated using the cold plate-Teflon block method and was compared with the junction-to-case thermal resistance (/spl theta//sub jc/) measurement method. Both thermal dice and real dice were prepared to measure the 119 BGA package thermal resistance. The junction-to-case and junction-to-top thermal resistance for a real die are about 3.5/spl deg/C/W and 3.8/spl deg/C/W respectively, whereas with a thermal die, the junction-to-case and junction-to-top thermal resistance are 4.0/spl deg/C/W and 4.8/spl deg/C/W respectively. For both thermal and real die, the junction-to-case thermal resistance is less than the junction-to-top thermal resistance. This is attributed to the different thermal boundary conditions applied to the 119 BGA package for each test method. In the meantime, thermal resistances of packages with thermal dice were approximately 14.3/spl sim/26.3% higher than those of package with real dice, the reason for which is being investigated.","PeriodicalId":253023,"journal":{"name":"Fifteenth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (Cat. No.99CH36306)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120989923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Thermal modeling of diamond-based power electronics packaging","authors":"P. Fabis, D. Shum, H. Windischmann","doi":"10.1109/STHERM.1999.762434","DOIUrl":"https://doi.org/10.1109/STHERM.1999.762434","url":null,"abstract":"Finite element modeling suggests that the thermal performance of plastic and ceramic packages could be significantly improved through the insertion of CVD diamond substrates. The model was formulated by considering the thermal properties, dimensions, and spatial locations of the materials comprising the dominant conductive thermal path. Optimized designs were selected, targeting the minimization of die junction temperature, package maximum temperature, and package temperature gradients through the reduction of the heat source to heat sink thermal resistance. Selected designs were fabricated and thermally evaluated using infrared thermometry. Diamond-enhanced package designs using leadframe-substrate \"overlaps\" for plastic SOIC packages and through-flange \"inserts\" for ceramic power packages realized junction temperature decreases of greater than 50%.","PeriodicalId":253023,"journal":{"name":"Fifteenth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (Cat. No.99CH36306)","volume":"128 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116426360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Generation and verification of boundary independent compact thermal models for active components according to the DELPHI/SEED methods","authors":"H. Pape, G. Noebauer","doi":"10.1109/STHERM.1999.762449","DOIUrl":"https://doi.org/10.1109/STHERM.1999.762449","url":null,"abstract":"In the European project SEED (Supplier Evaluation and Exploitation of DELPHI), methods for thermal characterization of active components developed in DELPHI were evaluated by component suppliers. The methods were improved for practical application and extended to all IC package types. Test parts were chosen to cover as wide as possible a range of different plastic packages currently in use, including comparison of Alloy 42 (FeNi42) and Cu-based leadframe material, as well as a large and a small chip inside the same package, standard and thermally enhanced power devices, DSO, QFP and BGA packages. For all device types investigated, it was possible to generate simple resistor networks which reproduce junction temperatures and fluxes of a detailed finite element model for all 38 boundary conditions suggested in DELPHI with an average accuracy of 1-2%. Maximum errors are in general about 10% or less. As result of the SEED project, methods for thermal characterization of active components are available, which not only work in practice, but are also robust and low cost, because no test PCB is needed for measurements. Physically, they are much better suited to model validations than existing thermal resistance measurements. The resulting thermal resistor network allows end users for the first time to routinely predict the junction temperatures of components in their specific applications with an acceptable accuracy. The final goal of a simple and universal thermal characterization of electronic components is achieved. Standardization and adoption is in progress.","PeriodicalId":253023,"journal":{"name":"Fifteenth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (Cat. No.99CH36306)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128100514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Radmehr, K. Kelkar, P. Kelly, S. Patankar, S.S. Kang
{"title":"Analysis of the effect of bypass on the performance of heat sinks using flow network modeling (FNM)","authors":"A. Radmehr, K. Kelkar, P. Kelly, S. Patankar, S.S. Kang","doi":"10.1109/STHERM.1999.762427","DOIUrl":"https://doi.org/10.1109/STHERM.1999.762427","url":null,"abstract":"Heat sinks are used in electronics cooling systems to provide extra area for transfer of the heat dissipated by semiconductor devices. However, in presence of clearance regions around the heat sink, flow that would otherwise go through the heat sink bypasses it. This study uses the technique of flow network modeling (FNM) to analyze the effect of flow bypass on the heat transfer performance of a plate fin heat sink. The physical situation analyzed corresponds to a typical wind tunnel test cell used for characterization of the heat sink performance. Results of network analysis predict that increasing the bypass region has a strong effect on decreasing the flow rate through the heat sink. Therefore, the effectiveness of the heat sink is reduced when large clearance regions are present around it. The network analysis is shown to be very easy, quick, and accurate. It can be used for analysis of the placement of heat sinks in practical cooling systems.","PeriodicalId":253023,"journal":{"name":"Fifteenth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (Cat. No.99CH36306)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131836060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A computational study of two phase jet impingement cooling of an electronic chip","authors":"D. Wang, E. Yu, A. Przekwas","doi":"10.1109/STHERM.1999.762422","DOIUrl":"https://doi.org/10.1109/STHERM.1999.762422","url":null,"abstract":"A two phase model has been developed and demonstrated for jet impingement cooling of a silicon chip. The Eulerian two-fluid model is applied for resolution of boiling heat transfer of a phase-change coolant. The simulation result predicts the overall cooling performance and is in reasonably good agreement with the reported experimental data. The boiling effect is found to be more pronounced for natural convection cooling than for the jet impingement scheme. A saturation point of the boiling effect is also observed in the jet impingement case. An optimized flow rate has also been found for the impingement jet cooling of the chip considered.","PeriodicalId":253023,"journal":{"name":"Fifteenth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (Cat. No.99CH36306)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132445470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Evaluation of airflow prediction methods in compact electronic enclosures","authors":"Rebecca Biswas, Raghu, Agarwal, Avijit Goswami","doi":"10.1109/STHERM.1999.762428","DOIUrl":"https://doi.org/10.1109/STHERM.1999.762428","url":null,"abstract":"In forced convection cooled electronic enclosure design, one of the most important parameters is enclosure airflow. Enclosure airflow mainly depends upon enclosure pressure drop and fan characteristics. Fan curves are often used in conjunction with system pressure drop (impedance) characteristics to determine airflow. CFD tool accuracy depends mainly on accurate modeling of system pressure loss (grilles, filters, etc.) and fan curve data accuracy. The fan curves, which show fan air delivery capacity at various pressure drops, are usually generated with no obstructions close to the fan. However, electronic systems contain densely packaged components, including airflow obstructions such as inlet and outlet grilles in close proximity to the fan, so methods using fan curves can often be inaccurate for airflow prediction. Inaccuracies can also occur by using grille pressure loss data from handbooks. The objective of this study is to understand the accuracy of airflow prediction methods use pressure loss and fan curve data compared to experimental results obtained in a wind tunnel. The system used is representative of typical electronic systems, which include major components such as fans, inlet and outlet grilles and an array of stacked PCBs. Further components such as capacitors, inductors, transformers and heat sinks are also included to increase the total pressure drop. Base configuration variations are made by changing grille open area, fan size and using fans in series and parallel configurations. It is found that differences of up to 20% can occur depending on the method used to calculate flow.","PeriodicalId":253023,"journal":{"name":"Fifteenth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (Cat. No.99CH36306)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114968904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Measurements of adhesive bondline effective thermal conductivity and thermal resistance using the laser flash method","authors":"R. Campbell, S.E. Smith, R. Dietz","doi":"10.1109/STHERM.1999.762433","DOIUrl":"https://doi.org/10.1109/STHERM.1999.762433","url":null,"abstract":"Thermal modeling of device packages requires accurate thermophysical property data for package materials. Accurate data for the thermal resistance of the adhesive bondline used to attach a high power device to a substrate is critical because this thermal resistance can be a significant part of the total thermal resistance in the heat flow path from the device junction to the package case or ambient. The bondline thermal resistance can in principle be calculated by dividing the expected or measured bondline thickness by the adhesive thermal conductivity measured on a free-standing cured sample. However, at a typical bondline thickness of 15-75 /spl mu/m, the contact thermal resistance between the adhesive and its adherents can be significant compared to the intrinsic thermal resistance of the adhesive and thus cannot be ignored. Also, the thermal conductivity measured on a free-standing cured sample may not be equivalent to the thermal conductivity of the adhesive in the bonded assembly. This paper investigates some of the variables that determine adhesive bondline effective thermal conductivity and contact resistance. The results of multilayer laser flash diffusivity measurements are presented for a range of available adhesives in \"sandwich\" sample assemblies that simulate the package. Thermal conductivity measurements of the free-standing adhesives are also obtained by the laser flash method.","PeriodicalId":253023,"journal":{"name":"Fifteenth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (Cat. No.99CH36306)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134242496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}