Fifteenth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (Cat. No.99CH36306)最新文献

Experimental validation of numerical heat transfer predictions for singleand multi-component printed circuit boards in natural convection environments 自然对流环境下单组分和多组分印刷电路板数值传热预测的实验验证

Fifteenth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (Cat. No.99CH36306) Pub Date : 1999-03-09 DOI: 10.1109/STHERM.1999.762429

P. Rodgers, V. Eveloy, J. Lohan, Carl-Magnus Fager, P. Tiilikka, J. Rantala

{"title":"Experimental validation of numerical heat transfer predictions for singleand multi-component printed circuit boards in natural convection environments","authors":"P. Rodgers, V. Eveloy, J. Lohan, Carl-Magnus Fager, P. Tiilikka, J. Rantala","doi":"10.1109/STHERM.1999.762429","DOIUrl":"https://doi.org/10.1109/STHERM.1999.762429","url":null,"abstract":"Increasing power densities and changing component design have increased the need for accurate prediction of temperature effects that may affect system performance or reliability. To highlight these aspects early in the product development cycle, designers resort to using computational fluid dynamics (CFD) based numerical predictive tools. However, users acknowledge that these predictions require experimental verification which is now readily available during the early design phase. Therefore, a need exists to establish well-defined benchmark test cases to help establish confidence in both modelling methodology and numerical tools. This paper presents such information for three package types (SO16, TSOP48, and PQFP208) which are evaluated on single and multi-component PCBs. Benchmark criteria are based on the prediction of steady state component junction temperature and associated component-PCB surface temperature gradients, which are both compared with experimental measurements. While the detailed numerical models typically predicted junction temperature to within 4/spl deg/C, discrepancies as great as 9/spl deg/C were also recorded. The sensitivity of prediction accuracy was assessed against discretization level and both the thermal conductivity and geometry of package materials. Hence it was considered important that all experimental and numerical modelling details be provided for reference.","PeriodicalId":253023,"journal":{"name":"Fifteenth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (Cat. No.99CH36306)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128496025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 25

Compact thermal models of conduction cooled packages 传导冷却封装的紧凑热模型

Fifteenth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (Cat. No.99CH36306) Pub Date : 1999-03-09 DOI: 10.1109/STHERM.1999.762452

A. Ortega, A. Aranyosi, R. Griffin, S. West, D. Edwards

{"title":"Compact thermal models of conduction cooled packages","authors":"A. Ortega, A. Aranyosi, R. Griffin, S. West, D. Edwards","doi":"10.1109/STHERM.1999.762452","DOIUrl":"https://doi.org/10.1109/STHERM.1999.762452","url":null,"abstract":"An extensive study was performed with the aim of developing compact thermal models of a variety of electronic packages used in conduction cooled scenarios. A nonredundant set of boundary conditions suitable for generation of compact thermal models for packages cooled by conduction to the board was developed by formal mathematical principles. A design of experiments method was used to reduce this set to four conditions allowing the creation of CTMs that were independent of board and underfill characteristics. The accuracy of CTM generation by applying external resistances representative of underfill and board resistances was critically examined. The technique was found to be convenient for optimizing the model parameters on both junction temperatures and heat flows through the prime lumped areas. Detailed thermal models of about thirty components, representing thirteen different package types, were created from physical component data extracted from X-ray, SEM and high-power microscopy images. Using optimization techniques allowing constrained nonlinear global optimization, compact models of different network topologies were generated for all the packages. To optimize the thermal networks, a genetic algorithm-based commercial code was employed in a standard spreadsheet environment. It was found that for most of the packages only network topologies that included a floating node provided satisfactory accuracy for both the junction temperatures and heat flows through the prime lumped areas.","PeriodicalId":253023,"journal":{"name":"Fifteenth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (Cat. No.99CH36306)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126267487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Thermal design for flip chip on board in natural convection 板上倒装芯片自然对流散热设计

Fifteenth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (Cat. No.99CH36306) Pub Date : 1999-03-09 DOI: 10.1109/STHERM.1999.762438

Chul-Bee Hwang

{"title":"Thermal design for flip chip on board in natural convection","authors":"Chul-Bee Hwang","doi":"10.1109/STHERM.1999.762438","DOIUrl":"https://doi.org/10.1109/STHERM.1999.762438","url":null,"abstract":"In this paper, thermal features of flip chip on FR4 boards with different control variables are discussed. The control variables include die size, board construction, bump pattern, underfill material and inclusion of a heat spreader. Thermal paths are analyzed to determine the heat dissipation mechanism. Due to the decreased package surface for direct flip chip on board, the junction to ambient thermal resistance is significantly dominated by the carrier board, differing with values for conventional large size packages. Therefore, apart from the thermal resistance value acquired from standard measurements, more package performance information is needed for the system designer. Accordingly, the maximum device junction temperature and power dissipation limit of the package are chosen to establish package thermal design guidelines. The three-resistor network model can determine the solution satisfying the junction and board temperature constraints. This study projects the thermal performance limits of flip chip. An experimentally validated computational fluid dynamics model is used for the flip chip on board thermal design. The die size, board construction and heat spreader inclusion are vital performance factors. As the junction-to-board resistance is small, the board temperature constraint decides the allowable flip chip power dissipation. With fixed die size in applications, an enhancement applying a heat spreader is essential when using a low conductivity carrier board. The methodology in this study can be used for other package design tasks, especially for future small packages.","PeriodicalId":253023,"journal":{"name":"Fifteenth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (Cat. No.99CH36306)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131809796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Thermal parameter estimation in the presence of uncertainty [packaging] 存在不确定度的热参数估计[包装]

Fifteenth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (Cat. No.99CH36306) Pub Date : 1999-03-09 DOI: 10.1109/STHERM.1999.762425

A. Emery

引用次数: 1

Thermal management using "dry" phase change material 热管理使用“干”相变材料

Fifteenth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (Cat. No.99CH36306) Pub Date : 1999-03-09 DOI: 10.1109/STHERM.1999.762432

R. Wirtz, N. Zheng, D. Chandra

引用次数: 38

FMI applied to the study of the temperature distribution in flip chips FMI应用于倒装芯片温度分布的研究

Fifteenth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (Cat. No.99CH36306) Pub Date : 1999-03-09 DOI: 10.1109/STHERM.1999.762444

N. Boyer, D. Masson, M. Meunier, M. Simard-Normandin

引用次数: 1

Sub-millisecond thermal impedance and steady state thermal resistance explored [power MOSFETs] 亚毫秒级热阻抗和稳态热阻研究[功率mosfet]

Fifteenth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (Cat. No.99CH36306) Pub Date : 1999-03-09 DOI: 10.1109/STHERM.1999.762445

J.W. Worman

引用次数: 6

A review of IBM sponsored research and development projects for computer cooling 回顾IBM赞助的计算机冷却研究和开发项目

Fifteenth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (Cat. No.99CH36306) Pub Date : 1999-03-09 DOI: 10.1109/STHERM.1999.762443

R. C. Chu

引用次数: 21

Thermal conductivity homogeneity and topography characterization 导热均匀性及形貌表征

Fifteenth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (Cat. No.99CH36306) Pub Date : 1999-03-09 DOI: 10.1109/STHERM.1999.762436

N. Mathis, M. deSorgo

引用次数: 3

New way for thermal transient testing [IC packaging] 热瞬态测试新方法[IC封装]

Fifteenth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (Cat. No.99CH36306) Pub Date : 1999-03-09 DOI: 10.1109/STHERM.1999.762446

V. Székely, M. Rencz, A. Poppe, B. Courtois

引用次数: 17