2020 IEEE International Test Conference (ITC)最新文献_第3页

qATG: Automatic Test Generation for Quantum Circuits 量子电路的自动测试生成

2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325228

Chen-Hung Wu, Cheng-Yun Hsieh, Jiun-Yun Li, C. Li

引用次数: 2

Flip-flops fanout splitting in scan designs 扫描设计中的触发器扇出分裂

2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325247

M. Ladnushkin

引用次数: 0

X-Tolerant Tunable Compactor for In-System Test 用于系统内测试的x公差可调压实机

2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325266

Yingdi Liu, Sylwester Milewski, Grzegorz Mrugalski, N. Mukherjee, J. Rajski, J. Tyszer, Bartosz Włdarczak

{"title":"X-Tolerant Tunable Compactor for In-System Test","authors":"Yingdi Liu, Sylwester Milewski, Grzegorz Mrugalski, N. Mukherjee, J. Rajski, J. Tyszer, Bartosz Włdarczak","doi":"10.1109/ITC44778.2020.9325266","DOIUrl":"https://doi.org/10.1109/ITC44778.2020.9325266","url":null,"abstract":"There is a growing number of integrated circuits that deploy hybrid test schemes combining on-chip test compression with logic BIST, with both techniques working synergistically to deliver high quality tests. As their architectural differences are gradually blurring, and both schemes efficiently share test logic, they become more vulnerable to unknown (X) states whose sources vary from uninitialized memory elements to unwrapped-for-test analog modules. Typically, X values degrade test results, and thus test response compaction schemes must be duly protected. This paper presents maXpress – an X-tolerant programmable compactor deploying a new scan chain selection mechanism capable of completely (as required by many in-system test applications) masking X states within redefinable groups of scan chains and designated scan shift cycles. In addition to the new architecture, the paper proposes an algorithm to automate maXpress control settings based on scan chain selection rules deployed to suppress X states. Experimental results obtained for a variety of industrial designs show feasibility and efficiency of the proposed scheme altogether with actual impact of X-masking on a resultant test coverage and test pattern counts.","PeriodicalId":251504,"journal":{"name":"2020 IEEE International Test Conference (ITC)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132451769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Design Optimization for N-port RF Network Reflectometers under Noise and Gain Imperfections 噪声和增益缺陷下n口射频网络反射计的设计优化

2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325256

Muslum Emir Avci, S. Ozev

引用次数: 1

Industrial Application of IJTAG Standards to the Test of Big-A/little-d devices IJTAG标准在大a /小d器件测试中的工业应用

2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325267

Hans Martin von Staudt, Mohamed Anas Benhebibi, J. Rearick, M. Laisne

{"title":"Industrial Application of IJTAG Standards to the Test of Big-A/little-d devices","authors":"Hans Martin von Staudt, Mohamed Anas Benhebibi, J. Rearick, M. Laisne","doi":"10.1109/ITC44778.2020.9325267","DOIUrl":"https://doi.org/10.1109/ITC44778.2020.9325267","url":null,"abstract":"IJTAG (IEEE 1687) has proven to successfully address the challenge of test integration for “digital instruments” in digital systems on chip (SoCs). Yet, beyond SoCs, mixed signal IP presents an even bigger obstacle. This is particularly true for so-called Big-A/little-d chips, which have a significant number of analog IP blocks whose integration makes meeting fast test development cycle time requirements, from silicon to test program readiness, a challenge. Also, these chips rarely include a JTAG TAP for access to test data registers (TDRs) on scan chains. Instead, they have very simple serial interfaces, like $I^{2}C$ or SPI, and these are the only form of communication with the system and, consequently, with the ATE. This paper demonstrates the principles of test generation for a Power Management Integrated Circuit (PMIC) using the Procedure Description Language (PDL) of the P1687.2 standard. The authors show how a test procedure for a medium complexity analog block, an LDO (Low Drop Out regulator) can be retargeted and transformed to the chip top level and from there to the ATE test programs. The typical test infrastructure of the PMIC is modelled in ICL, the InterConnect Language of the IEEE standards 1687, P1687.1 and P1687.2. In addition, the employment of the P1687.1 callbacks enables transparent access of test registers via transformations through the serial communication interface.","PeriodicalId":251504,"journal":{"name":"2020 IEEE International Test Conference (ITC)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129448470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Functional Test Sequences for Inducing Voltage Droops in a Multi-Threaded Processor 多线程处理器中感应电压下降的功能测试序列

2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325271

V. K. Kalyanam, E. Mahurin, M. Spence, J. Abraham

{"title":"Functional Test Sequences for Inducing Voltage Droops in a Multi-Threaded Processor","authors":"V. K. Kalyanam, E. Mahurin, M. Spence, J. Abraham","doi":"10.1109/ITC44778.2020.9325271","DOIUrl":"https://doi.org/10.1109/ITC44778.2020.9325271","url":null,"abstract":"Precisely controlled power delivery is critical for high performance systems-on-chip. This work describes functional test sequences to induce large dynamic and static supply voltage droops impacting the minimum operating voltage (VMIN) of the processor. An algorithm is provided to generate high and low power sequences that are functions targeting a wide range of power delivery network (PDN) frequencies. The voltagedroop tests induce large dynamic voltage droops by aligning hardware threads using a method that generates relatively prime sequence lengths across threads in a multi-threaded processor system. Functional tests also create symmetric and asymmetric high and low power sequences, introducing delay in processor pipeline stages. Additionally, tests consisting of a loop of sustained high-power sequences are also generated causing static droops. Simulation and silicon results of voltage-droop tests applied on a multi-threaded Qualcomm® Hexagon™ processor show that the techniques increase the VMIN of the processor system by up to 120 mV. Evaluation of the relatively prime method against the previously published NOP insertion method shows that the sequences generated using the relatively prime method can induce a higher rate of change of maximum dynamic voltage droop in $sim 72.5$% of functional test sequences.","PeriodicalId":251504,"journal":{"name":"2020 IEEE International Test Conference (ITC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133177270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Concurrent Detection of Failures in GPU Control Logic for Reliable Parallel Computing 面向可靠并行计算的GPU控制逻辑故障并发检测

2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325216

Hiroaki Itsuji, T. Uezono, Tadanobu Toba, Kojiro Ito, M. Hashimoto

{"title":"Concurrent Detection of Failures in GPU Control Logic for Reliable Parallel Computing","authors":"Hiroaki Itsuji, T. Uezono, Tadanobu Toba, Kojiro Ito, M. Hashimoto","doi":"10.1109/ITC44778.2020.9325216","DOIUrl":"https://doi.org/10.1109/ITC44778.2020.9325216","url":null,"abstract":"The reliability of GPUs is becoming a major concern due to the increased probability of failures and the high vulnerability of GPUs compared to conventional CPUs in terms of tasks per failure. While there are extensive countermeasures against failures in GPU data units, there are fewer countermeasures for failures in GPU control logics. Currently, software-based techniques, such as inserting signature codes for detecting GPU control-logic failures by comparing the expected signature value with the current signature value, are being utilized. However, in the conventional software-based techniques, application calculations, signature calculations, and signature comparison calculations are executed in sequence, which degrades the application throughputs. We have developed a software-based technique that concurrently detects GPU control-logic failures in a running application while largely maintaining its throughput. Experimental results show that when our technique concurrently executed application calculations, signature calculations, and signature comparison calculations for a matrix multiplication application, the application throughput remains 78% of the original one, whereas 62% is reported in literature. We also developed fault injection simulators specialized for injecting GPU-specific control-logic faults into GPU intermediate codes and found that 100% of GPU-specific failures could be detected both during and after application execution. The proposed approach can be utilized for a wide variety of safety-and reliability-critical applications.","PeriodicalId":251504,"journal":{"name":"2020 IEEE International Test Conference (ITC)","volume":"128 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123444733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Unleashing the Power of Anomaly Data for Soft Failure Predictive Analytics 为软故障预测分析释放异常数据的力量

2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325243

Fei Su, P. Goteti, Min Zhang

引用次数: 0

Quick Analyses for Improving Reliability and Functional Safety of Mixed-Signal ICs 提高混合信号集成电路可靠性和功能安全性的快速分析

2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325230

S. Sunter, Michał Wolinski, Anthony Coyette, Ronny Vanhooren, Wim Dobbelaere, Nektar Xama, Jhon Gomez, G. Gielen

引用次数: 1

Cross-PUF Attacks on Arbiter-PUFs through their Power Side-Channel 通过功率侧信道对仲裁puf的跨puf攻击

2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325241

Trevor Kroeger, Wei Cheng, S. Guilley, J. Danger, Naghmeh Karimi

{"title":"Cross-PUF Attacks on Arbiter-PUFs through their Power Side-Channel","authors":"Trevor Kroeger, Wei Cheng, S. Guilley, J. Danger, Naghmeh Karimi","doi":"10.1109/ITC44778.2020.9325241","DOIUrl":"https://doi.org/10.1109/ITC44778.2020.9325241","url":null,"abstract":"The silicon primitives known as Physically Unclonable Functions (PUFs) are used for various security purposes including key generation, device authentication, etc. Due to the imperfections in manufacturing process, PUFs produce their unique outputs (responses) for given input signals (challenges) fed to identical circuitry designs. Although PUFs are deployed to preserve security and are assumed to be unclonable, their functionality may still be compromised by modeling attacks. However, such attacks only target one single PUF aiming at reversing its behavior (based on a subset of its challengeresponse pairs), and are not useful for attacking other PUFs. Moreover a subset of the target PUF’s response has to be known by the attacker. This paper moves one step forward and investigates the possibility of Cross-PUF attacks in which a particular PUF’s power fingerprints can be used to break another PUF’s security. In these Cross-PUF attacks, the attacker has at his disposal a reference PUF, and uses its power side-channel to train a machine learning model which can be deployed to attack other identical PUFs. The experimental results show the high success of the proposed attacks even in presence of noise and temperature differences between the target PUF and the one used to train the model. We target arbiter-PUFs but we deduce that the findings extend to all its derivatives, e.g., XOR-PUFs and Feed-Forward-PUFs.","PeriodicalId":251504,"journal":{"name":"2020 IEEE International Test Conference (ITC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117109431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6