Functional Test Sequences for Inducing Voltage Droops in a Multi-Threaded Processor

Abstract

Precisely controlled power delivery is critical for high performance systems-on-chip. This work describes functional test sequences to induce large dynamic and static supply voltage droops impacting the minimum operating voltage (VMIN) of the processor. An algorithm is provided to generate high and low power sequences that are functions targeting a wide range of power delivery network (PDN) frequencies. The voltagedroop tests induce large dynamic voltage droops by aligning hardware threads using a method that generates relatively prime sequence lengths across threads in a multi-threaded processor system. Functional tests also create symmetric and asymmetric high and low power sequences, introducing delay in processor pipeline stages. Additionally, tests consisting of a loop of sustained high-power sequences are also generated causing static droops. Simulation and silicon results of voltage-droop tests applied on a multi-threaded Qualcomm® Hexagon™ processor show that the techniques increase the VMIN of the processor system by up to 120 mV. Evaluation of the relatively prime method against the previously published NOP insertion method shows that the sequences generated using the relatively prime method can induce a higher rate of change of maximum dynamic voltage droop in $\sim 72.5$% of functional test sequences.