2020 IEEE International Test Conference (ITC)最新文献

Methods for Susceptibility Analysis of Logic Gates in the Presence of Single Event Transients 单事件瞬态存在下逻辑门的敏感性分析方法

2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325252

R. Schvittz, P. Butzen, L. Rosa

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引用次数: 1

Hardware IP Protection Using Logic Encryption and Watermarking 使用逻辑加密和水印的硬件IP保护

2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325223

R. Karmakar, S. Chattopadhyay

{"title":"Hardware IP Protection Using Logic Encryption and Watermarking","authors":"R. Karmakar, S. Chattopadhyay","doi":"10.1109/ITC44778.2020.9325223","DOIUrl":"https://doi.org/10.1109/ITC44778.2020.9325223","url":null,"abstract":"Logic encryption is a popular Design-for-Security(DfS) solution that offers protection against the potential adversaries in the third-party fab labs and end-users. However, over the years, logic encryption has been a target of several attacks, especially Boolean satisfiability attacks. This paper exploits SAT attack’s inability of deobfuscating sequential circuits as a defense against it. We propose several strategies capable of preventing the SAT attack by obfuscating the scan-based Design-for-Testability (DfT) infrastructure. Unlike the existing SAT-resilient schemes, the proposed techniques do not suffer from poor output corruption for wrong keys. This paper also offers various probable solutions for inserting the key-gates into the circuit that ensures protection against numerous other attacks, which exploit weak key-gate locations. Along with several gate-level obfuscation strategies, this paper also presents a Cellular Automata (CA) guided FSM obfuscation strategy to offer protection at a higher abstraction level, that is, RTL-level. For all the proposed schemes, rigorous security analysis against various attacks evaluates their strengths and limitations. Testability analysis also ensures that none of the proposed techniques hamper the basic testing properties of the ICs. We also present a CA-based FSM watermarking strategy that helps to detect potential theft of the designer’s IP by any adversary.","PeriodicalId":251504,"journal":{"name":"2020 IEEE International Test Conference (ITC)","volume":"41 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120854012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Rapid PLL Monitoring By A Novel min-MAX Time-to-Digital Converter 一种新型最小-最大时间-数字转换器的快速锁相环监测

2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325217

Wei-Hao Chen, Chu-Chun Hsu, Shi-Yu Huang

引用次数: 4

MBIST Supported Multi Step Trim for Reliable eMRAM Sensing MBIST支持的多步骤修剪可靠的eMRAM传感

2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325218

Jong-Yun Yun, B. Nadeau-Dostie, Martin Keim, Lori Schramm, C. Dray, E. M. Boujamaa, Khushal Gelda

{"title":"MBIST Supported Multi Step Trim for Reliable eMRAM Sensing","authors":"Jong-Yun Yun, B. Nadeau-Dostie, Martin Keim, Lori Schramm, C. Dray, E. M. Boujamaa, Khushal Gelda","doi":"10.1109/ITC44778.2020.9325218","DOIUrl":"https://doi.org/10.1109/ITC44778.2020.9325218","url":null,"abstract":"Access Memory) has many attractive properties such as small size, fast operation speed, and good endurance. However, MRAM has a relatively small TMR (Tunneling Magnetoresistance) ratio, which means a small on-off state separation. It is a challenge to set an optimal reference resistance to reliably differentiate “1” and “0” states. Several trimming circuits were suggested in the literature to adjust a reference value and its search range. The trim setting can be controlled manually by user input; however, it consumes huge test time and requires off-chip engineering analysis to search and apply a trim setting for an individual memory array. In this paper, we will discuss the recent silicon results of fully automated trim process leveraging existing MBIST (Memory Built-in Self-Test) resources and new features to accommodate more complicated multi-step reference setting implementation through minor update of an existing MBIST circuit. The proposed MBIST solution uses a minimal number of tests to analyze massive array properties and automatically set complicated multi-step trim settings within a chip without the need for an external tester or manual adjustments.","PeriodicalId":251504,"journal":{"name":"2020 IEEE International Test Conference (ITC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124959450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Schmitt Trigger-Based Key Provisioning for Locking Analog/RF Integrated Circuits 基于Schmitt触发器的锁定模拟/射频集成电路密钥配置

2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325209

A. Sanabria-Borbón, N. G. Jayasankaran, S. Y. Lee, E. Sánchez-Sinencio, J. Hu, J. Rajendran

引用次数: 4

Knowledge Transfer for Diagnosis Outcome Preview with Limited Data 有限数据下诊断结果预览的知识转移

2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325214

Qicheng Huang, Chenlei Fang, R. D. Blanton

引用次数: 0

Functional Criticality Classification of Structural Faults in AI Accelerators 人工智能加速器结构故障的功能临界分类

2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325272

Arjun Chaudhuri, Jonti Talukdar, Fei Su, K. Chakrabarty

引用次数: 11

SPARTA: A Laser Probing Approach for Trojan Detection 斯巴达:一种用于特洛伊木马探测的激光探测方法

2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325222

Andrew Stern, Dhwani Mehta, Shahin Tajik, Farimah Farahmandi, M. Tehranipoor

{"title":"SPARTA: A Laser Probing Approach for Trojan Detection","authors":"Andrew Stern, Dhwani Mehta, Shahin Tajik, Farimah Farahmandi, M. Tehranipoor","doi":"10.1109/ITC44778.2020.9325222","DOIUrl":"https://doi.org/10.1109/ITC44778.2020.9325222","url":null,"abstract":"Integrated circuits (ICs) fabricated at untrusted foundries are vulnerable to hardware Trojan insertion. Trojans can be inserted into design files by modifying existing functionality or inserting additional circuitry into unused areas. Checking for the existence of Trojans either requires design-level modification or a complex test process. Unfortunately, the detection confidence using existing techniques is low, while they require a significant increase in verification effort, making them inapplicable to complex circuits due to aggressive time-to-market constraints. On the other hand, for a high confidence detection of Trojans, an exhaustive inspection may be required using destructive reverse-engineering techniques. However, such methods are quite expensive, render the device unusable, and are very time-consuming. In this work, we propose SPARTA, a non-destructive laser probing approach for Trojan detection, which detects sequential hardware Trojans by comparing clock activity within a fabricated IC with the original clock tree created in the design phase. SPARTA does not require any golden samples, but rather the golden design. SPARTA is based upon creating a 2-dimensional frequency map of the backside silicon using electro-optical frequency mapping (EOFM), which exposes the activity of clocked elements in the IC. The measurements are then compared with the expected sequential activity based on the original clock tree identified in the IC to detect all additions, subtractions, or modifications to sequential elements with sub-micron spatial resolution and its efficiency is demonstrated on a 28nm device.","PeriodicalId":251504,"journal":{"name":"2020 IEEE International Test Conference (ITC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115351810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Stress, Test, and Simulation of Analog IOs on Automotive ICs 汽车集成电路上模拟IOs的应力、测试和仿真

2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325224

Chen He, S. Traynor, Gayathri Bhagavatheeswaran, H. Sánchez

引用次数: 0

Data-driven fault model development for superconducting logic 数据驱动的超导逻辑故障模型开发

2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325220

Mingye Li, Fangzhou Wang, S. Gupta

引用次数: 3