2020 IEEE International Test Conference (ITC)最新文献_第2页

Streaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCs 流扫描网络(SSN):用于复杂soc测试的高效分组数据网络

2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325233

J. Cote, M. Kassab, W. Janiszewski, Ricardo Rodrigues, Reinhard Meier, Bartosz Kaczmarek, P. Orlando, G. Eide, J. Rajski, G. Colón-Bonet, N. Mysore, Ya Yin, P. Pant

{"title":"Streaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCs","authors":"J. Cote, M. Kassab, W. Janiszewski, Ricardo Rodrigues, Reinhard Meier, Bartosz Kaczmarek, P. Orlando, G. Eide, J. Rajski, G. Colón-Bonet, N. Mysore, Ya Yin, P. Pant","doi":"10.1109/ITC44778.2020.9325233","DOIUrl":"https://doi.org/10.1109/ITC44778.2020.9325233","url":null,"abstract":"System-on-Chip (SoC) designs are increasingly difficult to test using traditional scan access methods without incurring inefficient test time, high planning effort, and physical design/timing closure challenges. The number of cores keeps growing while chip pin counts available for scan remain constant or decline, limiting the ability to drive cores concurrently. With increasingly commonplace tiling and abutment, the scan distribution hardware must be placed inside the cores, making balanced pipelining when broadcasting to identical cores difficult. optimizing test time requires analyzing all the cores and subsequently changing the test hardware in the cores. Internal shift speed constraints may limit the ability to shift data in and out of the chip at high rates. Differences in pattern counts or scan chain lengths between cores tested in parallel can result in padding and increased test time. SSN is a bus-based scan data distribution architecture designed to address all these challenges. It enables simultaneous testing of any number of cores even with few chip I/Os. It facilitates short test time by enabling high-speed data distribution, by efficiently handling imbalances between cores, and by supporting testing of any number of identical cores with a constant cost. It provides a plug-and-play interface in each core that is well suited for abutted tiles, and simplifies scan timing closure. This paper also compares the test cost and implementation productivity of SSN with those of Intel’s Structural Test Fabric.","PeriodicalId":251504,"journal":{"name":"2020 IEEE International Test Conference (ITC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125422512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Online Fault Detection in ReRAM-Based Computing Systems by Monitoring Dynamic Power Consumption 基于动态功耗监测的rerram计算系统在线故障检测

2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325259

Mengyun Liu, K. Chakrabarty

引用次数: 3

Die-to-Die Testing and ECC Error Mitigation in Automotive and Industrial Safety Applications 汽车和工业安全应用中的模对模测试和ECC错误缓解

2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325242

Gabriele Boschi, Elisa Spano, H. Grigoryan, Arun Kumar, Gurgen Harutunyan

引用次数: 2

Improved Chain Diagnosis Methodology for Clock and Control Signal Defect Identification 时钟与控制信号缺陷识别的改进链诊断方法

2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325236

Bharath Nandakumar, Sameer Chillarige, Anil Malik, Atul Chabbra, Nicholai L'Esperance, Robert Redburn

引用次数: 0

Novel Eye Diagram Estimation Technique to Assess Signal Integrity in High-Speed Memory Test 基于眼图估计的高速记忆测试信号完整性评估方法

2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325279

Youngsu Oh, Dongmin Han, Byeongseon Go, Seungtaek Lee, Woosik Jeong

引用次数: 0

SAT-ATPG Generated Multi-Pattern Scan Tests for Cell Internal Defects: Coverage Analysis for Resistive Opens and Shorts SAT-ATPG生成的电池内部缺陷的多模式扫描测试:电阻开路和短路的覆盖分析

2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325240

Sujay Pandey, Zhiwei Liao, Shreyas Nandi, Sanya Gupta, S. Natarajan, Arani Sinha, A. Singh, A. Chatterjee

{"title":"SAT-ATPG Generated Multi-Pattern Scan Tests for Cell Internal Defects: Coverage Analysis for Resistive Opens and Shorts","authors":"Sujay Pandey, Zhiwei Liao, Shreyas Nandi, Sanya Gupta, S. Natarajan, Arani Sinha, A. Singh, A. Chatterjee","doi":"10.1109/ITC44778.2020.9325240","DOIUrl":"https://doi.org/10.1109/ITC44778.2020.9325240","url":null,"abstract":"Recent advances in process technology have resulted in novel defect mechanisms making the test generation process very challenging. In addition to complete opens and shorts that can be represented via extreme defect resistance magnitudes, partial resistive opens and shorts are also of concern in deeply scaled CMOS technologies. For open defects with intermediate defect magnitude values, it has been shown that multi-pattern tests are necessary for defect exposure. We extend this approach to short defects with intermediate defect magnitude values to obtain a suite of multi-pattern tests for standard cell instances that cover complete as well as partial intra-cell open and short defects. A hierarchical scan-compatible SAT-based test generation approach for full scan sequential circuits is then proposed that allows such multi-pattern tests to be applied to the circuit via the scan infrastructure. A key innovation is the combined use of shift and capture operations along with launch-on-capture and launch-on-shift scan based test application for increased defect coverage. Resulting defect coverage improvements over conventional two-pattern tests are demonstrated on ISCAS89 benchmark circuits.","PeriodicalId":251504,"journal":{"name":"2020 IEEE International Test Conference (ITC)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124429199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

A Weak Asynchronous RESet (ARES) PUF Using Start-up Characteristics of Null Conventional Logic Gates 利用零逻辑门启动特性的弱异步复位(ARES) PUF

2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325278

Sreeja Chowdhury, R. Y. Acharya, William Boullion, A. Felder, Mark Howard, J. Di, Domenic Forte

{"title":"A Weak Asynchronous RESet (ARES) PUF Using Start-up Characteristics of Null Conventional Logic Gates","authors":"Sreeja Chowdhury, R. Y. Acharya, William Boullion, A. Felder, Mark Howard, J. Di, Domenic Forte","doi":"10.1109/ITC44778.2020.9325278","DOIUrl":"https://doi.org/10.1109/ITC44778.2020.9325278","url":null,"abstract":"Physical unclonable functions (PUFs) are widely researched security primitive in the digital and analog domain but have yet to be explored for asynchronous circuits. In this paper, we propose novel optimization methods to design a weak Asynchronous RESet (ARES) PUF that exploits random start-up characteristics of Threshold M of N Null Conventional Logic (NCL) gates as a source of entropy. We employ two different methods to design the ARES PUF. The first includes traditional delay matching techniques using linear programming-based optimization, whereas the second one uses the genetic algorithm (GA) with delay matching as a fitness function. Both methodologies are explained with analysis and design specifications required to model NCL TH22 gates to achieve PUF characteristics. Threshold 2 of 2 (TH22) and 4 of 4 (TH44) gates are used as test cases for evaluation and comparison. Simulation results using initial delay matching techniques at 90nm and 65nm technology in HSPICE shows that the proposed ARES PUF has a uniqueness of 49.98% and reliability of 96.53% across $V_{DD} $ variation (± 10%) and 93.39% across temperature variation $(0^{circ}C- 80^{circ}C)$. Whereas, the GA method can optimize NCL cells to form a PUF with 49% uniqueness at 65nm with an average reliability of 96.4% across $V_{DD} $ and 93.82% across temperature. Preliminary silicon results for proposed TH22 at TSMC 90nm technology node shows a 34% improvement in uniqueness compared to standard TH22 gate with best-case uniqueness of 53.3% and reliability of 100% respectively across repeated measurements (noise). Unlike standard TH22, standard TH44 performs better with 47.62% best-case uniqueness and 98.1% reliability.1","PeriodicalId":251504,"journal":{"name":"2020 IEEE International Test Conference (ITC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116679429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Automating Design For Yield: Silicon Learning to Predictive Models and Design Optimization 自动化设计为产量:硅学习预测模型和设计优化

2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325263

S. Venkataraman, Pongpachara Limpisathian, P. Meinerzhagen, S. Natarajan, Eric Yang

引用次数: 2

TestDNA-E: Wafer Defect Signature for Pattern Recognition by Ensemble Learning 基于集成学习的晶圆缺陷特征模式识别

2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325237

L. Chen, Katherine Shu-Min Li, Ken Chau-Cheung Cheng, Sying-Jyan Wang, Andrew Yi-Ann Huang, Leon Chou, Nova Cheng-Yen Tsai, Chen-Shiun Lee

引用次数: 2

Automated Socket Anomaly Detection through Deep Learning 通过深度学习自动套接字异常检测

2020 IEEE International Test Conference (ITC) Pub Date : 2020-11-01 DOI: 10.1109/ITC44778.2020.9325269

Nidhi Agrawal, Min Yang, Constantinos Xanthopoulos, Vijayakumar Thangamariappan, Joe Xiao, Chee-Wah Ho, Keith Schaub, Ira Leventhal

引用次数: 1