Streaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCs

System-on-Chip (SoC) designs are increasingly difficult to test using traditional scan access methods without incurring inefficient test time, high planning effort, and physical design/timing closure challenges. The number of cores keeps growing while chip pin counts available for scan remain constant or decline, limiting the ability to drive cores concurrently. With increasingly commonplace tiling and abutment, the scan distribution hardware must be placed inside the cores, making balanced pipelining when broadcasting to identical cores difficult. optimizing test time requires analyzing all the cores and subsequently changing the test hardware in the cores. Internal shift speed constraints may limit the ability to shift data in and out of the chip at high rates. Differences in pattern counts or scan chain lengths between cores tested in parallel can result in padding and increased test time. SSN is a bus-based scan data distribution architecture designed to address all these challenges. It enables simultaneous testing of any number of cores even with few chip I/Os. It facilitates short test time by enabling high-speed data distribution, by efficiently handling imbalances between cores, and by supporting testing of any number of identical cores with a constant cost. It provides a plug-and-play interface in each core that is well suited for abutted tiles, and simplifies scan timing closure. This paper also compares the test cost and implementation productivity of SSN with those of Intel’s Structural Test Fabric.