Rapid PLL Monitoring By A Novel min-MAX Time-to-Digital Converter

Abstract

For a Phase-Locked Loop (PLL), the clock period variation is one important health condition indicator. In this paper, we present a rapid min-MAX period monitoring scheme for PLLs, using circuits made of only standard cells. The proposed scheme can monitor the clock period of a PLL ’s output clock signal continuously during a designated monitoring session, while reporting the minimum and maximum clock periods in a timely manner. As a result, performance hazards can be timely exposed and an alarm can be raised earlier. The most unique contribution in this work is the design of a novel min-MAX Time-to-Digital converter (TDC). We have implemented this monitoring scheme and integrated it with a cell-based PLL in a 90nm CMOS process and post-layout simulation is conducted to verify its effectiveness. Experimental results show that the proposed scheme is able to detect some dangerous conditions when the PLL ’s output clock signal exhibits abnormal clock cycle times due to some online transient fault.