Industrial Application of IJTAG Standards to the Test of Big-A/little-d devices

Abstract

IJTAG (IEEE 1687) has proven to successfully address the challenge of test integration for “digital instruments” in digital systems on chip (SoCs). Yet, beyond SoCs, mixed signal IP presents an even bigger obstacle. This is particularly true for so-called Big-A/little-d chips, which have a significant number of analog IP blocks whose integration makes meeting fast test development cycle time requirements, from silicon to test program readiness, a challenge. Also, these chips rarely include a JTAG TAP for access to test data registers (TDRs) on scan chains. Instead, they have very simple serial interfaces, like $I^{2}C$ or SPI, and these are the only form of communication with the system and, consequently, with the ATE. This paper demonstrates the principles of test generation for a Power Management Integrated Circuit (PMIC) using the Procedure Description Language (PDL) of the P1687.2 standard. The authors show how a test procedure for a medium complexity analog block, an LDO (Low Drop Out regulator) can be retargeted and transformed to the chip top level and from there to the ATE test programs. The typical test infrastructure of the PMIC is modelled in ICL, the InterConnect Language of the IEEE standards 1687, P1687.1 and P1687.2. In addition, the employment of the P1687.1 callbacks enables transparent access of test registers via transformations through the serial communication interface.