Flip-flops fanout splitting in scan designs

Abstract

Test point insertion is a key method of circuit modification for significant reduction of test patterns during an automatic test pattern generation in scan compression designs. This paper presents a new method of flip-flops replication in order to reduce test data volume and test application time by splitting the fanout of scan cells. This proposed approach employs fanout reduction and reconvergent fanout elimination in large nanometer designs. Experimental results on several IP-designs with embedded compression of test patterns show that the proposed method reduces test application time up to nearly 2 times with hardware costs not exceeding 2.5% of design area.